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公开(公告)号：US12056376B2
公开(公告)日：2024-08-06
申请号：US18144262
申请日：2023-05-08
申请人： Next Silicon Ltd
发明人： Yoav Lossin , Ron Schneider , Elad Raz , Ilan Tayari , Eyal Nagar
CPC分类号： G06F3/0635 , G06F3/0604 , G06F3/0683 , G06F13/4027 , G11C29/70
摘要： A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypassable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.
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公开(公告)号：US11630669B2
公开(公告)日：2023-04-18
申请号：US17406151
申请日：2021-08-19
申请人： Next Silicon Ltd
发明人： Elad Raz , Ilan Tayari
摘要： An apparatus for executing a software program, comprising processing units and a hardware processor adapted for: in an intermediate representation of the software program, where the intermediate representation comprises blocks, each associated with an execution block of the software program and comprising intermediate instructions, identifying a calling block and a target block, where the calling block comprises a control-flow intermediate instruction to execute a target intermediate instruction of the target block; generating target instructions using the target block; generating calling instructions using the calling block and a computer control instruction for invoking the target instructions, when the calling instructions are executed by a calling processing unit and the target instructions are executed by a target processing unit; configuring the calling processing unit for executing the calling instructions; and configuring the target processing unit for executing the target instructions.
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公开(公告)号：US11294686B1
公开(公告)日：2022-04-05
申请号：US17145490
申请日：2021-01-11
申请人： Next Silicon Ltd
发明人： Elad Raz , Ilan Tayari
摘要： An apparatus for computing, comprising a processing circuitry configured for computing an outcome of executing a set of computer instructions comprising a group of data variables, by: identifying an initial state of the processing circuitry; executing a set of anticipated computer instructions produced based on the set of computer instructions and a likely data value, where the likely data value is a value of one the group of data variables anticipated while executing the set of computer instructions; and when identifying, while executing the set of anticipated computer instructions, a failed prediction where the data variable is not equal to the likely data value: restoring the initial state of the processing circuitry; and executing a set of alternative computer instructions, produced based on the set of computer instructions and the at least one likely data value.
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公开(公告)号：US11176041B2
公开(公告)日：2021-11-16
申请号：US16054202
申请日：2018-08-03
申请人： Next Silicon Ltd
发明人： Elad Raz
IPC分类号： G06F12/0815 , G06F12/0893
摘要： A method for cache coherency in a reconfigurable cache architecture is provided. The method includes receiving a memory access command, wherein the memory access command includes at least an address of a memory to access; determining at least one access parameter based on the memory access command; and determining a target cache bin for serving the memory access command based in part on the at least one access parameter and the address.
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公开(公告)号：US11144238B1
公开(公告)日：2021-10-12
申请号：US17141267
申请日：2021-01-05
申请人： Next Silicon Ltd
发明人： Elad Raz , Yaron Dinkin
摘要： An apparatus for executing a software program, comprising at least one hardware processor configured for: identifying in a plurality of computer instructions at least one remote memory access instruction and a following instruction following the at least one remote memory access instruction; executing after the at least one remote memory access instruction a sequence of other instructions, where the sequence of other instructions comprises a return instruction to execute the following instruction; and executing the following instruction; wherein executing the sequence of other instructions comprises executing an updated plurality of computer instructions produced by at least one of: inserting into the plurality of computer instructions the sequence of other instructions or at least one flow-control instruction to execute the sequence of other instructions; and replacing the at least one remote memory access instruction with at least one non-blocking memory access instruction.
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公开(公告)号：US10817309B2
公开(公告)日：2020-10-27
申请号：US16053382
申请日：2018-08-02
申请人： Next Silicon Ltd
发明人： Elad Raz
摘要： A method for runtime optimization of a configurable processing architecture are disclosed. The method comprises receiving a plurality of calls for running at least one function; identifying at least one pattern among the plurality of received calls; and based on the at least one pattern, manipulating at least a portion of the configurable processing architecture, to compute the least one function.
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公开(公告)号：US12020069B2
公开(公告)日：2024-06-25
申请号：US17885642
申请日：2022-08-11
申请人： Next Silicon Ltd
发明人： Elad Raz , Ilan Tayari , Dan Shechter , Yuval Asher Deutsher
CPC分类号： G06F9/5016 , G06F9/5022 , G06F12/023 , G06F2209/5011
摘要： There is provided a computer implemented method of allocation of memory, comprising: issuing an allocation operation for allocation of a region of a pool of a memory by a first process executed on a first processor, sending a message to a second processor indicating the allocation of the region of the pool of the memory, wherein the first processor and the second processor access the region of the pool of the memory, issuing a free operation for release of the allocated region of the pool of the memory by a second process executed on a second processor, and releasing, by the first processor, the allocated region of the pool of the memory as indicated in the free operation, wherein the region of the pool of the memory allocated by the first process and released by the second process is a same region of memory.
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公开(公告)号：US11995419B1
公开(公告)日：2024-05-28
申请号：US18383537
申请日：2023-10-25
申请人： Next Silicon Ltd
发明人： Oshri Kdoshim , Elad Raz
CPC分类号： G06F8/34
摘要： There is provided a method, comprising simultaneously presenting in a GUI, a source code and an interactive graph of nodes connected by edges representing the source code mapped to physical configurable elements of computational cluster(s) of a processor each configurable to execute mathematical operations, each node represents operation(s) mapped to physical configurable elements, and edges represent dependencies between the operations, mapped to physical dependency links between the configurable elements, receiving, via the GUI, a user selection of a portion of the source code, determining node(s) and/or edge(s) of the interactive graph corresponding to the portion, and updating the GUI for visually distinguishing the node(s) and/or edge(s), wherein the visually distinguished node(s) represents a mapping to certain physical configurable elements and the visually distinguished edge(s) represents certain dependency links between the certain physical configurable elements of the processor configured to execute the user selected portion of the source code.
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公开(公告)号：US11720496B2
公开(公告)日：2023-08-08
申请号：US17504594
申请日：2021-10-19
申请人： Next Silicon Ltd.
发明人： Elad Raz
IPC分类号： G06F12/0815 , G06F12/0893
CPC分类号： G06F12/0815 , G06F12/0893 , G06F2212/1032 , G06F2212/601
摘要： A method for cache coherency in a reconfigurable cache architecture is provided. The method includes receiving a memory access command, wherein the memory access command includes at least an address of a memory to access; determining at least one access parameter based on the memory access command; and determining a target cache bin for serving the memory access command based in part on the at least one access parameter and the address.
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公开(公告)号：US11644990B2
公开(公告)日：2023-05-09
申请号：US17588352
申请日：2022-01-31
申请人： Next Silicon Ltd
发明人： Yoav Lossin , Ron Schneider , Elad Raz , Ilan Tayari , Eyal Nagar
CPC分类号： G06F3/0635 , G06F3/0604 , G06F3/0683 , G06F13/4027 , G11C29/70
摘要： A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypas sable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.
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