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公开(公告)号：US12197919B1
公开(公告)日：2025-01-14
申请号：US18744738
申请日：2024-06-17
Applicant: Next Silicon Ltd
Inventor： Elad Raz , Ilan Tayari , Itay Bookstein , Jonathan Lavi
Abstract: A system for executing a software program comprising processing units and a hardware processor configured to: for at least one set of blocks, each set comprising a calling block and a target block of an intermediate representation of the software program, generate control-transfer information describing at least one value of the software program at an exit of the calling block (out-value) and at least one other value of the software program at an entry to the target block (in-value); select a set of blocks according to at least one statistical value collected while executing the software program; generate a target set of instructions using the target block and the control-transfer information; generate a calling set of instructions using the calling block and the control-transfer information; configure a calling processing unit to execute the calling set of instructions; and configure a target processing unit to execute the target set of instructions.
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公开(公告)号：US11630669B2
公开(公告)日：2023-04-18
申请号：US17406151
申请日：2021-08-19
Applicant: Next Silicon Ltd
Inventor： Elad Raz , Ilan Tayari
Abstract: An apparatus for executing a software program, comprising processing units and a hardware processor adapted for: in an intermediate representation of the software program, where the intermediate representation comprises blocks, each associated with an execution block of the software program and comprising intermediate instructions, identifying a calling block and a target block, where the calling block comprises a control-flow intermediate instruction to execute a target intermediate instruction of the target block; generating target instructions using the target block; generating calling instructions using the calling block and a computer control instruction for invoking the target instructions, when the calling instructions are executed by a calling processing unit and the target instructions are executed by a target processing unit; configuring the calling processing unit for executing the calling instructions; and configuring the target processing unit for executing the target instructions.
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公开(公告)号：US11294686B1
公开(公告)日：2022-04-05
申请号：US17145490
申请日：2021-01-11
Applicant: Next Silicon Ltd
Inventor： Elad Raz , Ilan Tayari
Abstract: An apparatus for computing, comprising a processing circuitry configured for computing an outcome of executing a set of computer instructions comprising a group of data variables, by: identifying an initial state of the processing circuitry; executing a set of anticipated computer instructions produced based on the set of computer instructions and a likely data value, where the likely data value is a value of one the group of data variables anticipated while executing the set of computer instructions; and when identifying, while executing the set of anticipated computer instructions, a failed prediction where the data variable is not equal to the likely data value: restoring the initial state of the processing circuitry; and executing a set of alternative computer instructions, produced based on the set of computer instructions and the at least one likely data value.
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公开(公告)号：US12189412B2
公开(公告)日：2025-01-07
申请号：US18127719
申请日：2023-03-29
Applicant: Next Silicon Ltd
Inventor： Elad Raz , Ilan Tayari
Abstract: An apparatus for executing a software program, comprising processing units and a hardware processor adapted for: in an intermediate representation of the software program, where the intermediate representation comprises blocks, each associated with an execution block of the software program and comprising intermediate instructions, identifying a calling block and a target block, where the calling block comprises a control-flow intermediate instruction to execute a target intermediate instruction of the target block; generating target instructions using the target block; generating calling instructions using the calling block and a computer control instruction for invoking the target instructions, when the calling instructions are executed by a calling processing unit and the target instructions are executed by a target processing unit; configuring the calling processing unit for executing the calling instructions; and configuring the target processing unit for executing the target instructions.
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公开(公告)号：US12056376B2
公开(公告)日：2024-08-06
申请号：US18144262
申请日：2023-05-08
Applicant: Next Silicon Ltd
Inventor： Yoav Lossin , Ron Schneider , Elad Raz , Ilan Tayari , Eyal Nagar
CPC classification number: G06F3/0635 , G06F3/0604 , G06F3/0683 , G06F13/4027 , G11C29/70
Abstract: A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypassable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.
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Patent Agency Ranking
公开(公告)号：US11875153B1
公开(公告)日：2024-01-16
申请号：US18218152
申请日：2023-07-05
Applicant: Next Silicon Ltd
Inventor： Elad Raz , Ilan Tayari
IPC: G06F9/30
CPC classification number: G06F9/30123
Abstract: A system for processing a plurality of concurrent threads comprising: a reconfigurable processing grid, comprising logical elements and a context storage for storing thread contexts, each thread context for one of a plurality of concurrent threads, each implementing a dataflow graph comprising an identified operation; and a hardware processor configured for configuring the at reconfigurable processing grid for: executing a first thread of the plurality of concurrent threads; and while executing the first thread: storing a runtime context value of the first thread in the context storage; while waiting for completion of the identified operation by identified logical elements, executing the identified operation of a second thread by the identified logical element; and when execution of the identified operation of the first thread completes: retrieving the runtime context value of the first thread from the context storage; and executing another operation of the first thread.
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公开(公告)号：US11269526B2
公开(公告)日：2022-03-08
申请号：US16856072
申请日：2020-04-23
Applicant: Next Silicon Ltd
Inventor： Yoav Lossin , Ron Schneider , Elad Raz , Ilan Tayari , Eyal Nagar
Abstract: A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypassable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.
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公开(公告)号：US11113059B1
公开(公告)日：2021-09-07
申请号：US17172134
申请日：2021-02-10
Applicant: Next Silicon Ltd
Inventor： Elad Raz , Ilan Tayari
Abstract: An apparatus for executing a software program, comprising processing units and a hardware processor adapted for: in an intermediate representation of the software program, where the intermediate representation comprises blocks, each associated with an execution block of the software program and comprising intermediate instructions, identifying a calling block and a target block, where the calling block comprises a control-flow intermediate instruction to execute a target intermediate instruction of the target block; generating target instructions using the target block; generating calling instructions using the calling block and a computer control instruction for invoking the target instructions, when the calling instructions are executed by a calling processing unit and the target instructions are executed by a target processing unit; configuring the calling processing unit for executing the calling instructions; and configuring the target processing unit for executing the target instructions.
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公开(公告)号：US12020069B2
公开(公告)日：2024-06-25
申请号：US17885642
申请日：2022-08-11
Applicant: Next Silicon Ltd
Inventor： Elad Raz , Ilan Tayari , Dan Shechter , Yuval Asher Deutsher
CPC classification number: G06F9/5016 , G06F9/5022 , G06F12/023 , G06F2209/5011
Abstract: There is provided a computer implemented method of allocation of memory, comprising: issuing an allocation operation for allocation of a region of a pool of a memory by a first process executed on a first processor, sending a message to a second processor indicating the allocation of the region of the pool of the memory, wherein the first processor and the second processor access the region of the pool of the memory, issuing a free operation for release of the allocated region of the pool of the memory by a second process executed on a second processor, and releasing, by the first processor, the allocated region of the pool of the memory as indicated in the free operation, wherein the region of the pool of the memory allocated by the first process and released by the second process is a same region of memory.
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公开(公告)号：US11644990B2
公开(公告)日：2023-05-09
申请号：US17588352
申请日：2022-01-31
Applicant: Next Silicon Ltd
Inventor： Yoav Lossin , Ron Schneider , Elad Raz , Ilan Tayari , Eyal Nagar
CPC classification number: G06F3/0635 , G06F3/0604 , G06F3/0683 , G06F13/4027 , G11C29/70
Abstract: A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypas sable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.
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