公开(公告)号：US20070050548A1

公开(公告)日：2007-03-01

申请号：US11213165

申请日：2005-08-26

Applicant: Naveen Bali ,  Naresh Patel ,  Yasuhiro Endo

Inventor： Naveen Bali ,  Naresh Patel ,  Yasuhiro Endo

IPC: G06F12/00

CPC classification number: G06F12/0897 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/128 ,  Y02D10/13

Abstract: The present invention includes dynamically analyzing look-up requests from a cache look-up algorithm to look-up data block tags corresponding to blocks of data previously inserted into a cache memory, to determine a cache related parameter. After analysis of a specific look-up request, a block of data corresponding to the tag looked up by the look-up request may be accessed from the cache memory or from a mass storage device.

Abstract translation: 本发明包括动态地分析来自高速缓存查找算法的查找请求，以查找与先前插入到高速缓冲存储器中的数据块对应的数据块标签，以确定高速缓存相关参数。 在分析了特定查找请求之后，可以从高速缓冲存储器或大容量存储设备访问与由查找请求查找的标签相对应的数据块。

公开(公告)号：US08255630B1

公开(公告)日：2012-08-28

申请号：US12191272

申请日：2008-08-13

Applicant: Naveen Bali ,  Naresh Patel

Inventor： Naveen Bali ,  Naresh Patel

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0897 ,  G06F12/0866 ,  G06F12/126

Abstract: The present invention includes storing in a main memory data block tags corresponding to blocks of data previously inserted into a buffer cache memory and then evicted from the buffer cache memory or written over in the buffer cache memory. Counters associated with the tags are updated when look-up requests to look up data block tags are received from a cache look-up algorithm.

Abstract translation: 本发明包括在主存储器中存储对应于先前插入到缓冲高速缓冲存储器中的数据块的数据块标签，然后从缓冲器高速缓存存储器中逐出或写入缓冲器高速缓冲存储器中。 当从高速缓存查找算法接收到查找数据块标签的查询请求时，更新与标签相关联的计数器。

公开(公告)号：US07430639B1

公开(公告)日：2008-09-30

申请号：US11213274

申请日：2005-08-26

Applicant: Naveen Bali ,  Naresh Patel

Inventor： Naveen Bali ,  Naresh Patel

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0897 ,  G06F12/0866 ,  G06F12/126

Abstract: The present invention includes storing in a main memory data block tags corresponding to blocks of data previously inserted into a buffer cache memory and then evicted from the buffer cache memory or written over in the buffer cache memory. Counters associated with the tags are updated when look-up requests to look up data block tags are received from a cache look-up algorithm.

Abstract translation: 本发明包括在主存储器中存储对应于先前插入到缓冲高速缓冲存储器中的数据块的数据块标签，然后从缓冲器高速缓存存储器中逐出或写入缓冲器高速缓冲存储器中。 当从高速缓存查找算法接收到查找数据块标签的查询请求时，更新与标签相关联的计数器。

公开(公告)号：US07424577B2

公开(公告)日：2008-09-09

申请号：US11213165

申请日：2005-08-26

Applicant: Naveen Bali ,  Naresh Patel ,  Yasuhiro Endo

Inventor： Naveen Bali ,  Naresh Patel ,  Yasuhiro Endo

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0897 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/128 ,  Y02D10/13

Abstract: The present invention includes dynamically analyzing look-up requests from a cache look-up algorithm to look-up data block tags corresponding to blocks of data previously inserted into a cache memory, to determine a cache related parameter. After analysis of a specific look-up request, a block of data corresponding to the tag looked up by the look-up request may be accessed from the cache memory or from a mass storage device.

Abstract translation: 本发明包括动态地分析来自高速缓存查找算法的查找请求，以查找与先前插入到高速缓冲存储器中的数据块对应的数据块标签，以确定高速缓存相关参数。 在分析了特定查找请求之后，可以从高速缓冲存储器或大容量存储设备访问与由查找请求查找的标签相对应的数据块。

公开(公告)号：US08176251B2

公开(公告)日：2012-05-08

申请号：US12186507

申请日：2008-08-05

Applicant: Naveen Bali ,  Naresh Patel ,  Yasuhiro Endo

Inventor： Naveen Bali ,  Naresh Patel ,  Yasuhiro Endo

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F12/0897 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/128 ,  Y02D10/13

Abstract: The present invention includes dynamically analyzing look-up requests from a cache look-up algorithm to look-up data block tags corresponding to blocks of data previously inserted into a cache memory, to determine a cache related parameter. After analysis of a specific look-up request, a block of data corresponding to the tag looked up by the look-up request may be accessed from the cache memory or from a mass storage device.

Abstract translation: 本发明包括动态地分析来自高速缓存查找算法的查找请求，以查找与先前插入到高速缓冲存储器中的数据块对应的数据块标签，以确定高速缓存相关参数。 在分析了特定查找请求之后，可以从高速缓冲存储器或大容量存储设备访问与由查找请求查找的标签相对应的数据块。

公开(公告)号：US20080294846A1

公开(公告)日：2008-11-27

申请号：US12186507

申请日：2008-08-05

Applicant: Naveen Bali ,  Naresh Patel ,  Yasuhiro Endo

Inventor： Naveen Bali ,  Naresh Patel ,  Yasuhiro Endo

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/128 ,  Y02D10/13

Abstract: The present invention includes dynamically analyzing look-up requests from a cache look-up algorithm to look-up data block tags corresponding to blocks of data previously inserted into a cache memory, to determine a cache related parameter. After analysis of a specific look-up request, a block of data corresponding to the tag looked up by the look-up request may be accessed from the cache memory or from a mass storage device.

Abstract translation: 本发明包括动态地分析来自高速缓存查找算法的查找请求，以查找与先前插入到高速缓冲存储器中的数据块对应的数据块标签，以确定高速缓存相关参数。 在分析了特定查找请求之后，可以从高速缓冲存储器或大容量存储设备访问与由查找请求查找的标签相对应的数据块。

公开(公告)号：US08112585B2

公开(公告)日：2012-02-07

申请号：US12433758

申请日：2009-04-30

Applicant: Naresh Patel ,  Jeffrey S. Kimmel ,  Garth Goodson

Inventor： Naresh Patel ,  Jeffrey S. Kimmel ,  Garth Goodson

IPC: G06F12/06

CPC classification number: G06F12/121 ,  G06F12/0866 ,  G06F2212/601

Abstract: A method implements a cache-policy switching module in a storage system. The storage system includes a cache memory to cache storage data. The cache memory uses a first cache configuration. The cache-policy switching module emulates the caching of the storage data with a plurality of cache configurations. Upon a determination that one of the plurality of cache configurations performs better than the first cache configuration, the cache-policy switching module automatically applies the better performing cache configuration to the cache memory for caching the storage data.

Abstract translation: 一种方法在存储系统中实现高速缓存策略切换模块。 存储系统包括用于缓存存储数据的高速缓冲存储器。 缓存内存使用第一个缓存配置。 高速缓存策略交换模块利用多个高速缓存配置来模拟存储数据的高速缓存。 在确定多个高速缓存配置中的一个执行比第一高速缓存配置更好的情况下，高速缓存策略切换模块自动将更好执行的高速缓存配置应用于高速缓冲存储器以用于高速缓存存储数据。

公开(公告)号：US08015427B2

公开(公告)日：2011-09-06

申请号：US11738841

申请日：2007-04-23

Applicant: Steven C. Miller ,  Naresh Patel

Inventor： Steven C. Miller ,  Naresh Patel

IPC: G06F5/06 ,  G06F1/00 ,  G06F9/30

CPC classification number: G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  G06F9/3869 ,  G06F9/3891 ,  Y02D10/126

Abstract: A system and method for prioritization of clock rates in a multi-core processor is provided. Instruction arrival rates are measured during a time interval Ti−1 to Ti by a monitoring module either internal to the processor or operatively interconnected with the processor. Using the measured instruction arrival rates, the monitoring module calculates an optimal instruction arrival rate for each core of the processor. For processors that support continuous frequency changes for cores, each core is then set to an optimal service rate. For processors that only support a discrete set of arrival rates, the optimal rates are mapped to a closest supported rate and the cores are set to the closest supported rate. This procedure is then repeated for each time interval.

Abstract translation: 提供了一种用于在多核处理器中优先化时钟速率的系统和方法。 指令到达率在时间间隔Ti-1至Ti期间由处理器内部或与处理器可操作地互连的监视模块测量。 使用测量的指令到达率，监视模块为处理器的每个核心计算最佳指令到达速率。 对于支持内核连续频率更改的处理器，每个核心然后设置为最佳服务速率。 对于仅支持离散到达率集合的处理器，最优速率被映射到最接近的支持速率，并且核心被设置为最接近的支持速率。 然后每个时间间隔重复该过程。

公开(公告)号：US20100281216A1

公开(公告)日：2010-11-04

申请号：US12433758

申请日：2009-04-30

Applicant: Naresh Patel ,  Jeffrey S. Kimmel ,  Garth Goodson

Inventor： Naresh Patel ,  Jeffrey S. Kimmel ,  Garth Goodson

IPC: G06F12/08

CPC classification number: G06F12/121 ,  G06F12/0866 ,  G06F2212/601

Abstract: A method implements a cache-policy switching module in a storage system. The storage system includes a cache memory to cache storage data. The cache memory uses a first cache configuration. The cache-policy switching module emulates the caching of the storage data with a plurality of cache configurations. Upon a determination that one of the plurality of cache configurations performs better than the first cache configuration, the cache-policy switching module automatically applies the better performing cache configuration to the cache memory for caching the storage data.

Abstract translation: 一种方法在存储系统中实现高速缓存策略切换模块。 存储系统包括用于缓存存储数据的高速缓冲存储器。 缓存内存使用第一个缓存配置。 高速缓存策略交换模块利用多个高速缓存配置来模拟存储数据的高速缓存。 在确定多个高速缓存配置中的一个执行比第一高速缓存配置更好的情况下，高速缓存策略切换模块自动将更好执行的高速缓存配置应用于高速缓冲存储器以用于高速缓存存储数据。

公开(公告)号：US06389017B1

公开(公告)日：2002-05-14

申请号：US09211696

申请日：1998-12-14

Applicant: Naresh Patel ,  Karim Harzallah

Inventor： Naresh Patel ,  Karim Harzallah

IPC: H04L1228

CPC classification number: H04L47/26 ,  H04L45/00 ,  H04L45/245 ,  H04L47/125 ,  H04L47/50 ,  H04L47/627 ,  H04L49/101 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/505

Abstract: A system and method for scheduling packets between multiple links of an adaptive set utilizes a destination register or a cache line associated with each of the alternate links of the network switch. Each of the cache lines holds the destination of the last packet that used the link. Upon arrival, a packet associatively checks the content of all cache lines. If it hits, then it uses the corresponding link; otherwise, the packet is scheduled according to a round-robin policy or other default policy.

Abstract translation: 用于在自适应集合的多个链路之间调度分组的系统和方法利用与网络交换机的每个替代链路相关联的目的地寄存器或高速缓存行。 每个缓存行保存使用链接的最后一个数据包的目的地。 到达时，分组关联地检查所有高速缓存行的内容。 如果它命中，则使用相应的链接; 否则，根据循环策略或其他默认策略来调度分组。