公开(公告)号：US20110261084A1

公开(公告)日：2011-10-27

申请号：US12859888

申请日：2010-08-20

Applicant: Nang-Ping TU ,  Fu-Lung HSUEH ,  Mingo LIU

Inventor： Nang-Ping TU ,  Fu-Lung HSUEH ,  Mingo LIU

IPC: G09G3/36 ,  H03M1/06 ,  G09G5/10 ,  H03M1/66

CPC classification number: G09G3/3696 ,  G09G3/3688 ,  G09G2310/027 ,  H03M1/687 ,  H03M1/72 ,  H03M1/76 ,  H03M1/804 ,  H03M1/806

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract translation: 用于响应于M位数字输入代码输出模拟电压的两级数模转换器包括具有高参考电压输入节点的两位串行电荷再分配数模转换器，用于接收高电平 参考电压和用于接收低参考电压的低参考电压输入节点，以及电压选择器。 电压选择器将高参考电压和低参考电压设置为所选电平，这取决于至少一部分M位数字输入代码。

公开(公告)号：US20120218132A1

公开(公告)日：2012-08-30

申请号：US13466608

申请日：2012-05-08

Applicant: Nang-Ping TU ,  Fu-Lung HSUEH ,  Mingo LIU ,  I-Fey WANG

Inventor： Nang-Ping TU ,  Fu-Lung HSUEH ,  Mingo LIU ,  I-Fey WANG

IPC: H03M1/66

CPC classification number: H03M1/66 ,  G09G3/3648 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0294 ,  H03M1/662 ,  H03M1/765

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.

Abstract translation: 集成电路包括数模转换器（DAC）电路，其包括至少一个第一通道类型DAC和至少一个第二通道类型DAC。 集成电路包括多个采样和保持（S / H）电路。 每个S / H电路与DAC电路耦合。 S / H电路能够从DAC电路接收信号并并行输出信号。

公开(公告)号：US20130342247A1

公开(公告)日：2013-12-26

申请号：US13530136

申请日：2012-06-22

Applicant: Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Fu-Lung HSUEH

Inventor： Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Fu-Lung HSUEH

IPC: H03L7/08

CPC classification number: H03L7/103 ,  H03L7/097 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/18 ,  H03L2207/06

Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

Abstract translation: 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

公开(公告)号：US20120230457A1

公开(公告)日：2012-09-13

申请号：US13045788

申请日：2011-03-11

Applicant: Chan-Hong CHERN ,  Chih-Chang LIN ,  Ming-Chieh HUANG ,  Fu-Lung HSUEH

Inventor： Chan-Hong CHERN ,  Chih-Chang LIN ,  Ming-Chieh HUANG ,  Fu-Lung HSUEH

IPC: H04L7/00

CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/113 ,  H04L7/0337

Abstract: A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.

Abstract translation: 时钟和数据恢复（CDR）电路包括被配置为产生具有时钟频率的时钟信号的电感器 - 电容器压控振荡器（LCVCO）。 延迟锁定环（DLL）被配置为从LCVCO接收时钟信号并生成多个时钟相位。 电荷泵配置为控制LCVCO。 相位检测器被配置为从DLL接收数据输入和多个时钟相位，并且控制第一电荷泵以便对准数据输入和多个时钟相位的数据沿。

公开(公告)号：US20120146747A1

公开(公告)日：2012-06-14

申请号：US12967160

申请日：2010-12-14

Applicant: Po-Yi WU ,  Hsieh-Hung HSIEH ,  Ho-Hsiang CHEN ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

Inventor： Po-Yi WU ,  Hsieh-Hung HSIEH ,  Ho-Hsiang CHEN ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC: H03B19/00

CPC classification number: H03B19/00

Abstract: A millimeter-wave wideband frequency doubler stage for use in a distributed frequency doubler includes: a differential input pair of transistors, each transistor having respective gate, drain and source terminals, wherein the source terminals are coupled together to a first power supply node and the drain terminals are coupled together at a first node to a second power supply node; first and second pairs of bandpass gate lines coupled to the gate terminals of the transistors; and a pair of bandpass drain lines coupled to the drain terminals of the transistors.

Abstract translation: 用于分布式倍频器的毫米波宽带倍频器级包括：差分输入对晶体管，每个晶体管具有相应的栅极，漏极和源极端子，其中源极端子耦合到第一电源节点，并且 漏极端子在第一节点耦合到第二电源节点; 耦合到晶体管的栅极端子的第一和第二对带通栅极线; 以及耦合到晶体管的漏极端子的一对带通漏极线。

公开(公告)号：US20120044008A1

公开(公告)日：2012-02-23

申请号：US12859456

申请日：2010-08-19

Applicant: Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Chih-Chang LIN ,  Yuwen SWEI ,  Ming-Chieh HUANG

Inventor： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Chih-Chang LIN ,  Yuwen SWEI ,  Ming-Chieh HUANG

IPC: H03L5/00

CPC classification number: H03K3/02 ,  H03K19/018521 ,  H03K19/018528

Abstract: A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.

Abstract translation: 电平移位器包括输入节点，输出节点，上拉晶体管，下拉晶体管以及耦合在上拉晶体管和下拉晶体管之间的至少一个二极管连接器件。 电平移位器被布置为耦合到高电源电压，以在输入节点处接收具有第一电压电平的输入信号，并且在输出节点处提供具有第二电压电平的输出信号。 高电源电压高于第一电压电平。 所述至少一个二极管连接的装置允许输出信号被上拉到大约低于高电源电压的第一二极管电压降和/或被下拉到大约地面上的第二二极管电压降。 第一二极管电压降和第二二极管压降来自至少一个二极管连接的器件。

公开(公告)号：US20110215420A1

公开(公告)日：2011-09-08

申请号：US12766972

申请日：2010-04-26

Applicant: Fu-Lung HSUEH ,  Chih-Ping Chao ,  Chewn-Pu Jou ,  Yung-Chow Peng ,  Harry-Hak-Lay Chuang ,  Kuo-Tung Sung

Inventor： Fu-Lung HSUEH ,  Chih-Ping Chao ,  Chewn-Pu Jou ,  Yung-Chow Peng ,  Harry-Hak-Lay Chuang ,  Kuo-Tung Sung

IPC: H01L27/088 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/50 ,  G06F17/5009 ,  H01L27/088 ,  H01L27/0922

Abstract: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.

Abstract translation: MOS器件包括具有第一和第二触点的有源区。 第一和第二栅极设置在第一和第二触点之间。 第一门被设置成与第一接触相邻并且具有第三接触。 第二栅极被设置成与第二触点相邻并且具有耦合到第三触点的第四触点。 由有源区和第一栅极限定的晶体管具有第一阈值电压，并且由有源区和第二栅极限定的晶体管具有第二阈值电压。

公开(公告)号：US20130311957A1

公开(公告)日：2013-11-21

申请号：US13475853

申请日：2012-05-18

Applicant: Chih-Hsien CHANG ,  Yung-Chow PENG ,  Fu-Lung HSUEH

Inventor： Chih-Hsien CHANG ,  Yung-Chow PENG ,  Fu-Lung HSUEH

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/00 ,  G06F17/5009 ,  G06F17/5045 ,  G06F17/5068 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

Abstract: A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information.

Abstract translation: 电路设计系统包括被配置为产生电路的示意图信息和预着色信息的示意性设计工具。 电路设计系统还包括被配置为在非暂时计算机可读介质上存储原理图信息和预着色信息的网表文件，以及被配置为从网表文件中提取预着色信息的提取工具。 包括在电路设计系统中的布局设计工具被配置为基于原理图信息和预着色信息设计至少一个掩模。 电路设计系统还包括布局与示意性比较工具，其被配置为将至少一个掩模与示意图信息和预着色信息进行比较。

公开(公告)号：US20120266126A1

公开(公告)日：2012-10-18

申请号：US13084748

申请日：2011-04-12

Applicant: Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Li-Chun TIEN

Inventor： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Li-Chun TIEN

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of designing an integrated circuit includes providing a cell library including a first and second cell structures. The cell structures each include a dummy gate electrode disposed on a boundary. An edge gate electrode is disposed adjacent to the dummy gate electrode. An oxide definition (OD) region has an edge disposed between the edge gate electrode and the dummy gate electrode. The method includes determining if the cell structures are to be abutted with each other. If so, the method includes abutting the cell structures. If not so, the method includes increasing areas of portions of the OD regions between the edge gate electrodes and the dummy gate electrodes.

Abstract translation: 设计集成电路的方法包括提供包括第一和第二单元结构的单元库。 电池结构各自包括设置在边界上的虚拟栅电极。 边缘栅电极被设置成与虚拟栅电极相邻。 氧化物定义（OD）区域具有设置在边缘栅电极和伪栅电极之间的边缘。 该方法包括确定单元结构是否彼此邻接。 如果是，则该方法包括邻接单元结构。 如果不是这样，则该方法包括增加边缘栅极电极和虚拟栅电极之间的OD区域的部分区域。

公开(公告)号：US20120019302A1

公开(公告)日：2012-01-26

申请号：US12843479

申请日：2010-07-26

Applicant: Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Ming-Chieh HUANG ,  Chih-Chang LIN

Inventor： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Ming-Chieh HUANG ,  Chih-Chang LIN

IPC: H03L5/00

CPC classification number: H03K19/018521

Abstract: A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.

Abstract translation: 电平移位器包括一个PMOS和两个NMOS晶体管。 第一NMOS晶体管的源极耦合到低电源电压。 输入信号耦合到第一NMOS晶体管的栅极和第二NMOS晶体管的源极。 输入信号具有高达第一电源电压的电压电平。 PMOS晶体管的源极耦合到高于第一电源电压的第二电源电压。 输出信号耦合在PMOS和第一NMOS晶体管之间。 第一NMOS晶体管被布置为当输入信号为逻辑1时下拉输出信号，并且第二NMOS晶体管被布置为使得PMOS晶体管能够以第二电源电压将输出信号上拉至逻辑1， 输入信号为逻辑0。