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公开(公告)号：US20210286389A1
公开(公告)日：2021-09-16
申请号：US17249717
申请日：2021-03-10
申请人： NXP USA, Inc.
发明人： Jiawei Fu , Jianzhou Wu , Jie Jin , Yikun Mo , Stefano Pietri
摘要： A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.
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公开(公告)号：US12028086B2
公开(公告)日：2024-07-02
申请号：US17819092
申请日：2022-08-11
申请人： NXP USA, INC.
发明人： Yizhong Zhang , Jie Jin , Stefano Pietri , Michael Todd Berens , Hongyan Yao , Jiawei Fu
CPC分类号： H03M1/1057 , H03M1/66 , H03M1/687 , H03M1/765 , H03M1/785
摘要： A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fL based on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fL with a high frequency clock having a constant frequency fH. A memory is included to store at least two counter values generating by comparing fL and fH once when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.
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公开(公告)号：US11979169B2
公开(公告)日：2024-05-07
申请号：US17812542
申请日：2022-07-14
申请人： NXP USA, Inc.
发明人： Yizhong Zhang , Stefano Pietri , Jie Jin , Michael Todd Berens
摘要： A digital to analog converter (DAC) includes an amplifier including a buffer of the DAC, and a resistor ladder arrangement coupled to a non-inverting input terminal of the amplifier to generate a voltage based on a digital control word. The arrangement includes a first, least-significant bit, segment arranged in one of an R-2R or unit-R configuration, a second, most-significant bit, segment including one or more units each including a second-segment-resistor having a resistor terminal coupled to a respective second switch and having a second resistance, RMSB, and a third segment including one or more third-segment-resistors coupled in parallel to the non-inverting input terminal and connected to a first reference voltage terminal. M2 designates a number of bits in the digital control word for controlling the second switches, and the third segment has a total resistance, Rsp, based on M2.
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公开(公告)号：US20230066987A1
公开(公告)日：2023-03-02
申请号：US17819092
申请日：2022-08-11
申请人： NXP USA, INC.
发明人： Yizhong Zhang , Jie Jin , Stefano Pietri , Michael Todd Berens , Hongyan Yao , Jiawei Fu
IPC分类号： H03M1/10
摘要： A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fL based on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fL with a high frequency clock having a constant frequency fH. A memory is included to store at least two counter values generating by comparing fL and fH once when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.
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公开(公告)号：US10659013B2
公开(公告)日：2020-05-19
申请号：US16237727
申请日：2019-01-01
申请人： NXP USA, INC.
发明人： Yang Wang , Jianzhou Wu , Jie Jin , Jiawei Fu
摘要： A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.
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公开(公告)号：US11709517B2
公开(公告)日：2023-07-25
申请号：US17249717
申请日：2021-03-10
申请人： NXP USA, Inc.
发明人： Jiawei Fu , Jianzhou Wu , Jie Jin , Yikun Mo , Stefano Pietri
CPC分类号： G05F3/205 , G05F3/262 , H01L27/0629 , H01L27/0802 , H01L28/20 , H01L29/8605
摘要： A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.
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公开(公告)号：US20230031469A1
公开(公告)日：2023-02-02
申请号：US17812542
申请日：2022-07-14
申请人： NXP USA, Inc.
发明人： Yizhong Zhang , Stefano Pietri , Jie Jin , Michael Todd Berens
摘要： A digital to analog converter (DAC) includes an amplifier including a buffer of the DAC, and a resistor ladder arrangement coupled to a non-inverting input terminal of the amplifier to generate a voltage based on a digital control word. The arrangement includes a first, least-significant bit, segment arranged in one of an R-2R or unit-R configuration, a second, most-significant bit, segment including one or more units each including a second-segment-resistor having a resistor terminal coupled to a respective second switch and having a second resistance, RMSB, and a third segment including one or more third-segment-resistors coupled in parallel to the non-inverting input terminal and connected to a first reference voltage terminal. M2 designates a number of bits in the digital control word for controlling the second switches, and the third segment has a total resistance, Rsp, based on M2.
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公开(公告)号：US20190222201A1
公开(公告)日：2019-07-18
申请号：US16237727
申请日：2019-01-01
申请人： NXP USA, INC.
发明人： Yang Wang , Jianzhou Wu , Jie Jin , Jiawei Fu
IPC分类号： H03K3/0231 , H03L3/00 , H03L7/099
CPC分类号： H03K3/0231 , G05F3/262 , H03L3/00 , H03L7/0995
摘要： A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.
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