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1.发明申请SINGLE-WIRE INTERFACE BUS TRANSCIVER SYSTEM BASED ON I2C-BUS, AND ASSOCIATED METHOD FOR COMMUNICATION OF SINGLE-WIRE INTERFACE BUS 审中-公开基于I2C总线的单线接口总线交换机系统，以及单线接口总线通信的相关方法公开(公告)号：US20170024354A1
公开(公告)日：2017-01-26
申请号：US15301871
申请日：2015-04-09
Applicant: NXP B.V.
Inventor： Hongyun Zhang , Jian Qing , Zhongmeng Chen
IPC: G06F13/42 , G06F13/40 , G06F13/364
CPC classification number: G06F13/4291 , G06F13/364 , G06F13/387 , G06F13/404 , G06F13/4295
Abstract: There is disclosed a single-wire Interface bus transceiver system comprising: an I2C master, a master transceiver, a signal wire, a slave transceiver and an I2C slave, wherein the master transceiver is adapted to encode master data SDA and master clock SCL received from I2C master using Manchester code, generate master single wire signal and transfer it to the slave transceiver through the signal wire, the master transceiver is also adapted to decode Manchester-encoded slave signal received from the signal wire and transfer the decoded slave data to I2C master; the slave transceiver is adapted to encode slave data received from I2C slave using Manchester code, generate slave single wire signal and transfer it to the master transceiver through the signal wire, the slave transceiver is also adapted to decode Manchester-encoded master signal received from the signal wire, generate the recovered master clock and transfer the decoded master data and recovered master clock to I2C slave.
Abstract translation: 公开了一种单线接口总线收发器系统，包括：I2C主机，主收发器，信号线，从机收发器和I2C从机，其中主收发器适于编码主数据SDA和主时钟SCL从 I2C主机使用曼彻斯特码，生成主单线信号并通过信号线将其传输到从机收发器，主收发器还适用于解码从信号线接收的曼彻斯特编码的从机信号，并将解码的从属数据传输到I2C主机 ; 从机收发器适用于使用曼彻斯特码编码从I2C从机接收的从机数据，产生从机单线信号，并通过信号线将其传送到主收发器，从机收发器还适用于解码从主机收到的曼彻斯特编码的主信号 信号线，产生恢复的主时钟，并将解码的主数据和恢复的主时钟传送到I2C从机。
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公开(公告)号：US11296532B2
公开(公告)日：2022-04-05
申请号：US16243009
申请日：2019-01-08
Applicant: NXP B.V.
Abstract: A wireless battery charging system includes a trickle power device (e.g., FET) that generates a trickle charging current for charging a battery and a trickle charging regulator that controls the trickle power device. A fast charging device generates a fast charging current for charging the battery, where the fast charging current is greater than the trickle charging current. A fast charging regulator controls the fast charging device. A digital control module generates a trickle charging codeword to control the trickle charging regulator and a fast charging codeword to control the fast charging regulator. Each charging regulator has a programmable current mirror that generates a mirrored current signal based on a codeword from the digital control module. The digital control module instructs the charging regulators to control the power devices to operate in a trickle charging mode, a fast charging mode, and transitions between those modes.
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公开(公告)号：US10284074B2
公开(公告)日：2019-05-07
申请号：US15706763
申请日：2017-09-18
Applicant: NXP B.V.
Inventor： Mingliang Wan , Tinghua Yun , Jian Qing , Peter Christiaans
IPC: H02M1/32 , H02H7/122 , H01L27/02 , H03K17/06 , H02H3/18 , H02H9/04 , H03K17/30 , H03K17/16 , H03K17/041 , H03K17/04
Abstract: A load switch includes a switch element and first and second control circuits. The switch element has an input terminal for receiving an input voltage, an output terminal for providing an output voltage, and a control terminal for receiving a switch signal, which turns the switch element on and off. The first control circuit is connected to the control terminal of the switch element and turns off the switch element in response to a first control signal. The second control circuit also is connected to the control terminal of the switch element and keeps the switch element turned off, after the first control circuit has turned off the switch element.
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公开(公告)号：US09893607B1
公开(公告)日：2018-02-13
申请号：US15644811
申请日：2017-07-09
Applicant: NXP B.V.
Inventor： Mingliang Wan , Xindong Duan , Jian Qing
Abstract: A low drop-out voltage regulator (LDO) includes an LDO unit, a switch circuit, a charge pump, and an initiation circuit. The switch circuit is coupled to a voltage input terminal and outputs a selected input voltage. The LDO unit receives the selected input voltage from the switch circuit and generates a regulated output voltage. The charge pump is coupled to the LDO unit to receive the regulated output voltage, and generate a control signal that is provided to the switch circuit. The initiation circuit receives the input voltage and generates an initiation voltage that greater than the regulated output voltage. The initiation voltage is provided to the charge pump circuit, along with the regulated output voltage. The initiation voltage drives the charge pump circuit when the regulated output voltage is not large enough to drive the charge pump circuit.
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公开(公告)号：US11736005B2
公开(公告)日：2023-08-22
申请号：US17443972
申请日：2021-07-29
Applicant: NXP B.V.
Inventor： Dongyong Zhu , Bo Cai , XinDong Duan , Feng Cong , Jian Qing
Abstract: The disclosure relates to a switched capacitor converter (SCC) with gate driving circuits for limiting currents provided by switching field effect transistors. Embodiments disclosed include an SCC with gate driver curcuits providing gate voltage signals to power FETs, each gate driver circuit comprising first and second gate driver modules and configured to operate in: a first mode in which the first gate driver module provides a gate voltage signal to a power FET that switches between first and second voltage rails by operation of first and second switches connected between the pair of voltage rails; and a second mode in which, in reponse to enabling of a current limit switching signal, the first gate driver module disables switching of one of the first and second switches and the second gate driver module operates to limit a current provided to the power FET.
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Patent Agency Ranking
公开(公告)号：US10826482B1
公开(公告)日：2020-11-03
申请号：US16851054
申请日：2020-04-16
Applicant: NXP B.V.
Inventor： Kenneth Chung Yin Kwok , Suming Lai , Xuechu Li , Fuchun Zhan , Jian Qing
IPC: H03K17/00 , H03K17/082 , H01L29/788
Abstract: Aspects of the present disclosure are directed to circuitry to control a gate voltage. As may be implemented in accordance with one or more embodiments, a voltage level is controlled for a field effect transistor (FET) having a floating gate and a target operating voltage above which the FET would be overcharged and around which the FET has a nominal operating range. Pulse circuitry is configured to apply energy to the floating gate in pulses, in operation the applied energy being pulsed low relative to the gate's target operating voltage, and then being changed by adjusting successive pulses until the gate reaches the target operating voltage. A feedback circuit samples a voltage level of, and enables the pulse circuitry to apply pulsed energy to, the floating gate for directing operation of the FET based on the target operating voltage in the nominal operating range.
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公开(公告)号：US10693292B2
公开(公告)日：2020-06-23
申请号：US15678991
申请日：2017-08-16
Applicant: NXP B.V.
Inventor： Shenglan Tang , Jian Qing , Xindong Duan
Abstract: A surge protection circuit includes a DC trigger circuit that generates a trigger signal when a surge pulse occurs, and a surge protection device, coupled to the DC trigger circuit, that generates a clamp voltage as an output voltage of the surge protection circuit and conducts surge currents to ground in response to the trigger signal. A feedback circuit is provided between the surge protection device and the DC trigger circuit. The feedback circuit lowers the clamp voltage so that it does not exceed a failure voltage of the surge protection device.
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公开(公告)号：US20220385179A1
公开(公告)日：2022-12-01
申请号：US17443972
申请日：2021-07-29
Applicant: NXP B.V.
Inventor： Dongyong Zhu , Bo Cai , XinDong Duan , Feng Cong , Jian Qing
IPC: H02M3/07 , H03K17/16 , H03K17/0812 , H02M1/08 , H02M3/158
Abstract: The disclosure relates to a switched capacitor converter with gate driving circuits for limiting currents provided by switching field effect transistors. Embodiments disclosed include a switched capacitor converter (100), SCC, comprising a plurality of gate driver circuits (101a-d, 200, 300) arranged to provide a gate voltage signal to a respective power FET (102a-d) in response to a respective input switching signal (sw1_in, sw2_in, sw3_in, sw4_in, IN), wherein each gate driver circuit (101a-d, 200, 300) comprises a first gate driver module (206) and a second gate driver module (207), the gate driver circuit (101a-d, 200, 300) configured to operate in: a first mode in which the first gate driver module (206) provides the gate voltage signal to a respective power FET (102a-d, 205) in response to an input switching signal (IN) at an input (203) of the first gate driver module (206) causing the gate voltage signal to switch between first and second voltage rails (201, 202) by operation of first and second switches (208, 209) connected between the pair of voltage rails (201, 202); and a second mode in which, in response to enabling of a current limit switching signal (climit_en), the first gate driver module disables switching of one of the first and second switches (208, 209) and the second gate driver module (207) operates to limit a current provided to the respective power FET (102a-d, 205).
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公开(公告)号：US11165364B2
公开(公告)日：2021-11-02
申请号：US16283845
申请日：2019-02-25
Applicant: NXP B.V.
Inventor： Fuchun Zhan , Tinghua Yun , Jian Qing , Chao Chen , Li Zhang , Feng Cong
Abstract: A synchronous rectifier converts an AC input into a DC output. The synchronous rectifier has four switches controlled by four switch control modules. Each switch is connected between a different AC component and either the DC output or ground. Each switch control module has digitally assisted “switch on” circuitry that detects “on” bounces in the corresponding AC component to control when to turn on the corresponding switch and digitally assisted “switch off” circuitry that detects “off” bounces in the AC component to control when to turn off the corresponding switch. The “switch on” circuitry has a digitally assisted comparator to detect threshold crossings in the AC component, and the “switch off” circuitry has a digitally assisted programmable delay cell to turn off the switch for a predetermined duration following each detected threshold crossing.
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公开(公告)号：US10216690B2
公开(公告)日：2019-02-26
申请号：US15301871
申请日：2015-04-09
Applicant: NXP B.V.
Inventor： Hongyun Zhang , Jian Qing , Zhongmeng Chen
IPC: G06F13/00 , G06F13/42 , G06F13/364 , G06F13/40 , G06F13/38
Abstract: There is disclosed a single-wire Interface bus transceiver system comprising: an I2C master, a master transceiver, a signal wire, a slave transceiver and an I2C slave, wherein the master transceiver is adapted to encode master data SDA and master clock SCL received from I2C master using Manchester code, generate master single wire signal and transfer it to the slave transceiver through the signal wire, the master transceiver is also adapted to decode Manchester-encoded slave signal received from the signal wire and transfer the decoded slave data to I2C master; the slave transceiver is adapted to encode slave data received from I2C slave using Manchester code, generate slave single wire signal and transfer it to the master transceiver through the signal wire, the slave transceiver is also adapted to decode Manchester-encoded master signal received from the signal wire, generate the recovered master clock and transfer the decoded master data and recovered master clock to I2C slave.
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