公开(公告)号：US20240004705A1

公开(公告)日：2024-01-04

申请号：US17856368

申请日：2022-07-01

Applicant: NVIDIA Corporation

Inventor： Chad Robert Plummer ,  Pratikkumar Dilipkumar Patel ,  Jun Gu ,  Tao Li ,  Divya Ramakrishnan ,  Michael Houston

IPC: G06F9/48

CPC classification number: G06F9/4893

Abstract: A device comprises one or more circuits that dynamically adjust a load profile of one or more processing devices processing a workload in a bulk-synchronous mode.

公开(公告)号：US20220113789A1

公开(公告)日：2022-04-14

申请号：US17069172

申请日：2020-10-13

Applicant: Nvidia Corporation

Inventor： Benjamin Faulkner ,  Mini Rawat ,  Sreedhar Narayanaswamy ,  Tom Li ,  Swanand Bindoo ,  Divya Ramakrishnan

IPC: G06F1/3296 ,  G06T1/20 ,  G06F1/28 ,  G06F9/50

Abstract: A datacenter power management system and method is disclosed. A plurality of computing units are enabled to operate at a second frequency, higher than a first frequency, in response to determining from respective power coefficients for these computing units, that a power level at this higher frequency remains below a power budget

公开(公告)号：US20250155947A1

公开(公告)日：2025-05-15

申请号：US18886621

申请日：2024-09-16

Applicant: NVIDIA Corporation

Inventor： Benjamin D. Faulkner ,  Padmanabhan Kannan ,  Srinivasan Raghuraman ,  Peng Cheng Shen ,  Divya Ramakrishnan ,  Swanand Santosh Bindoo ,  Sreedhar Narayanaswamy ,  Amey Y. Marathe

IPC: G06F1/30 ,  G06F1/20 ,  G06F11/07

Abstract: Apparatuses, systems, and techniques to optimize processor performance. In at least one embodiment, a method increases an operation voltage of one or more processors, based at least in part, on one or more error rates of the one or more processors.

公开(公告)号：US20220240408A1

公开(公告)日：2022-07-28

申请号：US17155959

申请日：2021-01-22

Applicant: Nvidia Corporation

Inventor： Benjamin D. Faulkner ,  Mini Rawat ,  Tao Li ,  Divya Ramakrishnan ,  Swanand Santosh Bindoo ,  Sreedhar Narayanaswamy

IPC: H05K7/14 ,  G06T1/20 ,  G06F9/50

Abstract: A system to select graphics processing units (GPUs) to execute a task is disclosed. In at least one embodiment, GPUs are selected based on one or more task parameters and one or more fused parameters.

公开(公告)号：US20180123604A1

公开(公告)日：2018-05-03

申请号：US15340901

申请日：2016-11-01

Applicant: NVIDIA CORPORATION

Inventor： Tezaswi Raja ,  Ben Faulkner ,  Divya Ramakrishnan ,  Tao Liu ,  Veeramani V ,  Ayon Dey ,  Javid Aziz

IPC: H03L7/099 ,  H03L1/00 ,  H03L5/00

Abstract: Aspects of the present invention are directed to techniques for improving the efficiency of power supply schemes by continuously and adaptively scaling voltage and frequency levels in an integrated circuit based on measured conditions in real-time, without resorting to a reliance on excessive pre-computed margins typical of conventional schemes. Embodiments of the present invention employ a self-tuning dynamic voltage control oscillator (or other similar clock signal generator) that sets the frequency for components in the integrated circuit. When a requested frequency exceeds a maximum allowed frequency for a given voltage level (accounting for other age and temperature related conditions), a look-up table is dynamically referenced to determine a new voltage level that is sufficient to safely and efficiently generate the requested frequency. The look-up table continuously receives updates on the operating conditions, and new voltage requests can be generated dynamically as necessary based on the system's current needs.

公开(公告)号：US11971774B2

公开(公告)日：2024-04-30

申请号：US17069172

申请日：2020-10-13

Applicant: Nvidia Corporation

Inventor： Benjamin Faulkner ,  Mini Rawat ,  Sreedhar Narayanaswamy ,  Tom Li ,  Swanand Bindoo ,  Divya Ramakrishnan

IPC: G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3296 ,  G06F9/50 ,  G06T1/20

CPC classification number: G06F1/3296 ,  G06F1/28 ,  G06F9/5094 ,  G06T1/20

Abstract: A datacenter power management system and method is disclosed. A plurality of computing units are enabled to operate at a second frequency, higher than a first frequency, in response to determining from respective power coefficients for these computing units, that a power level at this higher frequency remains below a power budget.

公开(公告)号：US12124308B2

公开(公告)日：2024-10-22

申请号：US17848274

申请日：2022-06-23

Applicant: NVIDIA Corporation

Inventor： Benjamin D. Faulkner ,  Padmanabhan Kannan ,  Srinivasan Raghuraman ,  Peng Cheng Shen ,  Divya Ramakrishnan ,  Swanand Santosh Bindoo ,  Sreedhar Narayanaswamy ,  Amey Y. Marathe

IPC: G06F11/00 ,  G06F1/20 ,  G06F1/30 ,  G06F11/07

CPC classification number: G06F1/30 ,  G06F1/206 ,  G06F11/0721 ,  G06F11/076 ,  G06F11/0793

Abstract: Apparatuses, systems, and techniques to optimize processor performance. In at least one embodiment, a method increases an operation voltage of one or more processors, based at least in part, on one or more error rates of the one or more processors.

公开(公告)号：US20240094793A1

公开(公告)日：2024-03-21

申请号：US17848274

申请日：2022-06-23

Applicant: NVIDIA Corporation

Inventor： Benjamin D. Faulkner ,  Padmanabhan Kannan ,  Srinivasan Raghuraman ,  Peng Cheng Shen ,  Divya Ramakrishnan ,  Swanand Santosh Bindoo ,  Sreedhar Narayanaswamy ,  Amey Y. Marathe

IPC: G06F1/30 ,  G06F11/07

CPC classification number: G06F1/30 ,  G06F11/0721 ,  G06F11/076

Abstract: Apparatuses, systems, and techniques to optimize processor performance. In at least one embodiment, a method increases an operation voltage of one or more processors, based at least in part, on one or more error rates of the one or more processors.

公开(公告)号：US11487341B2

公开(公告)日：2022-11-01

申请号：US16460615

申请日：2019-07-02

Applicant: NVIDIA Corporation

Inventor： Aniket Naik ,  Tezaswi Raja ,  Kevin Wilder ,  Rajeshwaran Selvanesan ,  Divya Ramakrishnan ,  Daniel Rodriguez ,  Benjamin Faulkner ,  Raj Jayakar ,  Fei (Walter) Li

IPC: G06F1/324 ,  G06F9/38

Abstract: Systems and techniques for improving the performance of circuits while adapting to dynamic voltage drops caused by the execution of noisy instructions (e.g. high power consuming instructions) are provided. The performance is improved by slowing down the frequency of operation selectively for types of noisy instructions. An example technique controls a clock by detecting an instruction of a predetermined noisy type that is predicted to have a predefined noise characteristic (e.g. a high level of noise generated on the voltage rails of a circuit due to greater amount of current drawn by the instruction), and, responsive to the detecting, deceasing a frequency of the clock. The detecting occurs before execution of the instruction. The changing of the frequency in accordance with instruction type enables the circuits to be operated at high frequencies even if some of the workloads include instructions for which the frequency of operation is slowed down.

公开(公告)号：US20220113784A1

公开(公告)日：2022-04-14

申请号：US17068123

申请日：2020-10-12

Applicant: NVIDIA Corporation

Inventor： Jonah Matthew Alben ,  Benjamin D. Faulkner ,  Tao Li ,  Mini Rawat ,  Divya Ramakrishnan ,  Swanand Santosh Bindoo ,  Sreedhar Narayanaswamy

IPC: G06F1/3215 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3246

Abstract: Apparatuses, systems, and techniques to power balance multiple chips. In at least one embodiment, a system includes a plurality of processors having substantially equal performance capability and different power consumption capability, where a cumulative power consumption of the processors is not to exceed a system power threshold if each processor is operated at substantially peak performance.