公开(公告)号：US20040237023A1

公开(公告)日：2004-11-25

申请号：US10844556

申请日：2004-05-13

申请人： NEC Electronics Corporation

发明人： Hiroyuki Takahashi ,  Hiroshi Furuta

IPC分类号： G11C029/00

CPC分类号： G06F11/1008 ,  G06F2211/109 ,  G11C7/1006 ,  G11C7/24 ,  G11C11/406 ,  G11C11/4076 ,  G11C2207/2281 ,  G11C2207/229

摘要： In a memory system, an ECC circuit is not inserted on a data path for data writing/reading. The ECC process is performed during the cycle of normal data reading/writing process, in such timing that it does not conflict with the data reading/writing process in order not to cause a substantial delay in the data writing/reading process. Specifically, the ECC process is performed during the cycle of burst transfer in which a plurality of data are successively input to or output from a shift register. Since no access is made to the memory cell array during the burst transfer cycle, the ECC process does not cause a delay in the reading/writing process.

摘要翻译： 在存储器系统中，ECC电路不被插入用于数据写入/读取的数据路径上。 在正常数据读/写处理的周期期间，ECC处理是在与数据读/写处理不冲突的定时中进行的，以便不会导致数据写入/读取处理的实质延迟。 具体地说，在突发传送的周期中执行ECC处理，其中多个数据被连续地输入到移位寄存器或从移位寄存器输出。 由于在脉冲串传送周期期间不能对存储单元阵列进行访问，因此ECC处理不会导致读/写处理的延迟。

公开(公告)号：US20040081006A1

公开(公告)日：2004-04-29

申请号：US10691413

申请日：2003-10-22

申请人： NEC Electronics Corporation

发明人： Hiroyuki Takahashi

IPC分类号： G11C007/00

CPC分类号： G11C11/40603 ,  G11C11/406 ,  G11C11/40615

摘要： A semiconductor device have memory cell array including a plurality of memory cells, each of which includes first and second transistors and connected in series between a bit line for normal access only and a bit line for refreshing only, and a capacitor connected to a connection node at which the first and second transistors are tied. A word line for normal access only and a word line for refreshing only are connected to control terminals of the first and second transistors, respectively. The semiconductor memory device has a late-write configuration in which writing to a memory cell at an externally input write address is performed, being delayed by a predetermined number of write cycles exceeding at least one, and has at least a circuit for checking whether the write address externally input the predetermined number of write cycles earlier matches the refresh address. If there is no hit as a check result, a write operation for activating the word line for normal access, turning on the first transistor, and writing data and a refresh operation for activating the word line for refreshing only, and refreshing using a sense amplifier for refreshing only, connected to the bit line for refreshing only are performed concurrently.

摘要翻译： 半导体器件具有包括多个存储单元的存储单元阵列，每个存储单元包括第一和第二晶体管，并且串联连接在仅用于正常访问的位线和仅用于刷新的位线之间，以及连接到连接节点的电容器 其中第一和第二晶体管被连接。 仅用于正常访问的字线和仅用于刷新的字线分别连接到第一和第二晶体管的控制端子。 半导体存储器件具有后写入配置，其中执行外部输入写入地址对存储器单元的写入，延迟超过至少一个的预定数量的写入周期，并且至少有一个电路用于检查是否 写入地址外部输入预定数量的写入周期与刷新地址匹配。 如果没有作为检查结果的命中，则用于激活用于正常访问的字线，打开第一晶体管以及写入数据的写入操作和用于仅激活用于刷新的字线的刷新操作，以及使用读出放大器进行刷新 仅用于刷新，仅连接到位线才能刷新，并行执行。

公开(公告)号：US20040012412A1

公开(公告)日：2004-01-22

申请号：US10620659

申请日：2003-07-16

申请人： NEC Electronics Corporation

发明人： Hiroyuki Takahashi ,  Hiroyuki Satake

IPC分类号： H03K019/0175

CPC分类号： H03K5/086 ,  H03K5/1515 ,  H03K19/0013 ,  H03K2005/00136

摘要： A buffer circuit includes first and second transistors which are connected in series between first and second power supplies and which are controlled to be on/off based on values of signals at their control terminals are provided, in which a connection point between the two transistors is connected to an output terminal (OUT) and a control terminal of the first transistor is connected to an input terminal (IN), and a control circuit for performing on/off control over the second transistor based on an input signal from the input terminal (IN). The control circuit performs control so that when the input signal is at a second logic level corresponding to the second power supply, the second transistor is turned off, when the input signal goes to a first logic level corresponding to the first power supply, the second transistor is turned on to cause the output terminal (OUT) to a second power supply voltage, next, when the second transistor is turned off and then the input signal undergoes a transition from the first logic level to the second logic level and the first transistor switches from off to on, with the second transistor being kept off. A flip-flop is connected to the output terminal (OUT).

摘要翻译： 缓冲电路包括串联连接在第一和第二电源之间的第一和第二晶体管，并且根据控制端的信号值将其控制为导通/截止，其中两个晶体管之间的连接点为 连接到输出端子（OUT），并且第一晶体管的控制端子连接到输入端子（IN），以及控制电路，用于基于来自输入端子的输入信号来对第二晶体管进行导通/关断控制 在）。 控制电路进行控制，使得当输入信号处于与第二电源相对应的第二逻辑电平时，第二晶体管截止，当输入信号变为对应于第一电源的第一逻辑电平时，第二晶体管 晶体管导通以使输出端（OUT）达到第二电源电压，接下来，当第二晶体管截止，然后输入信号经历从第一逻辑电平转换到第二逻辑电平时，第一晶体管 从第二个晶体管关闭，从断开到关闭。 触发器连接到输出端（OUT）。

公开(公告)号：US20040079968A1

公开(公告)日：2004-04-29

申请号：US10692383

申请日：2003-10-23

申请人： NEC Electronics Corporation

发明人： Hiroyuki Takahashi

IPC分类号： H01L031/109

CPC分类号： G11C11/405 ,  G11C11/406 ,  G11C11/40603

摘要： A semiconductor memory device, which can hides a delay in a refresh operation from an outside for speeding up operation, comprises a memory cell including first and second transistors connected between a bit line for a write system and a bit line for a read system, and a capacitor C for data storage, in which a word line for a write system and a word line for a read system are connected to control terminals of the two transistors, respectively, a circuit for comparing a refresh address with an address selected according to a read/write signal among read/write addresses from an address holding circuit for holding input address signal and performing control so that if a mismatch is detected, a read/write operation using one of the read and write systems, selected by the read or write address and a refresh operation using the other of the read and write systems, selected by the refresh address are performed in parallel and if a match has been detected, the read or write operation using the word line and the bit line associated with one of the read and write systems is performed.

摘要翻译： 可以从外部隐藏刷新操作的延迟以加速操作的半导体存储器件包括存储单元，其包括连接在用于写入系统的位线和用于读取系统的位线之间的第一和第二晶体管，以及 用于数据存储的电容器C，其中写系统的字线和读系统的字线分别连接到两个晶体管的控制端，用于将刷新地址与根据 从地址保持电路读取/写入地址之间的读/写信号，用于保存输入地址信号并进行控制，以便如果检测到不匹配，则使用其中一个读取和写入系统的读/写操作，由读取或写入选择 并行执行使用由刷新地址选择的另一个读写系统的地址和刷新操作，并且如果已经检测到匹配，则使用th的读或写操作 e字线和与一个读取和写入系统相关联的位线被执行。

公开(公告)号：US20040076054A1

公开(公告)日：2004-04-22

申请号：US10683818

申请日：2003-10-10

申请人： NEC Electronics Corporation

发明人： Hiroyuki Takahashi

IPC分类号： G11C029/00

CPC分类号： G11C11/40603 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4061 ,  G11C2211/4067

摘要： A device has a bit line pair including first and second bit lines, a sense amplifier commonly connected to the bit line pair, and first and second cells connected at intersecting portions of first and second word lines and the first and second bit lines. In a normal mode, the first and second word lines are assigned separate addresses, whereas in a partial mode, the first and second word lines are assigned the same address. The first and second cells complimentarily store one bit of data. In storing a data in a first cell of two cells comprised in a twin cell into a second cell when set to the partial mode, the second word line is activated based on a trigger signal generated by a refresh timer during a precharge period for the bit line pair, and subsequently the precharge is completed. The first word line is then activated based on a delayed signal of the trigger signal, and the sense amplifier is activated to amplify a differential voltage between the bit line pair, so that the data of the first cell is written back into the first and second cells.

摘要翻译： 器件具有包括第一和第二位线的位线对，公共连接到位线对的读出放大器以及连接在第一和第二字线以及第一和第二位线的交叉部分的第一和第二单元。 在正常模式中，第一和第二字线被分配地址，而在部分模式中，第一和第二字线被分配相同的地址。 第一和第二个单元格补充地存储一位数据。 在设置为部分模式时，将包含在双胞胎中的两个单元的第一单元的数据存储到第二单元中，基于在该位的预充电周期期间由刷新定时器产生的触发信号来激活第二字线 线对，并且随后预充电完成。 然后基于触发信号的延迟信号激活第一字线，并且激活读出放大器以放大位线对之间的差分电压，使得第一单元的数据被写回到第一和第二 细胞。

公开(公告)号：US20040240288A1

公开(公告)日：2004-12-02

申请号：US10849906

申请日：2004-05-21

申请人： NEC Electronics Corporation

发明人： Hiroyuki Takahashi

IPC分类号： G11C007/00

CPC分类号： G11C11/40615 ,  G06F12/0893 ,  G06F2212/3042 ,  G11C7/1066 ,  G11C11/406 ,  G11C2207/107 ,  G11C2207/2245

摘要： A semiconductor memory device that does not delay read/write access due to a refresh and can be interface compatible with a high-speed SRAM such as a QDR SRAM, comprises a plurality of subarrays each having a plurality of dynamic memory cells; at least one cache memory for the plurality of subarrays; a circuit to check whether data read from the subarray selected by a read address is present in the cache memory or not; and a circuit performing control so that the check result indicates that the data is present in the cache memory, the data is read from the cache memory and refreshing of the subarray is performed concurrently with a read cycle.

摘要翻译： 一种半导体存储器件，其不会由于刷新而延迟读/写访问，并且可以与诸如QDR SRAM的高速SRAM接口兼容，包括多个子阵列，每个子阵列具有多个动态存储器单元; 用于所述多个子阵列的至少一个高速缓冲存储器; 用于检查从读取地址选择的子阵列读取的数据是否存在于高速缓冲存储器中的电路; 执行控制使得检查结果指示数据存在于高速缓冲存储器中的电路，从高速缓冲存储器读取数据，并且以读周期同时执行子阵列的刷新。

公开(公告)号：US20040032769A1

公开(公告)日：2004-02-19

申请号：US10639716

申请日：2003-08-12

申请人： NEC Electronics Corporation

发明人： Hiroyuki Takahashi ,  Yuuji Matsui ,  Masatoshi Sonoda ,  Yosiyuki Kato

IPC分类号： G11C029/00

CPC分类号： G11C11/419

摘要： A semiconductor storage device includes a circuit receiving a command signal for generating a read control signal (RPB) based on the transition of a clock signal CLK and a circuit receiving the command signal for generating a write control signal (WPB) based on the transition of the clock signal CLK. The read cycle in which decoding of an address, selection of a word line and activation of a sense amplifier are executed based on the read control signal to read cell data, and the write cycle in which decoding of an address, selection of a word line and activation of a write amplifier are executed based on the write control signal and bit line pre-charging is also carried out, are carried out alternately. The sense period of the read cycle is overlapped with the decoding period of the write cycle.

摘要翻译： 半导体存储装置包括：电路，接收基于时钟信号CLK的转变产生读取控制信号（RPB）的指令信号;以及接收用于生成写入控制信号（WPB）的指令信号的电路， 时钟信号CLK。 基于读取的控制信号来读取单元数据的地址的解码，字线的选择和读出放大器的激活的读取周期以及地址的解码，字线的选择 并且基于写控制信号执行写放大器的激活，并且还执行位线预充电，交替执行。 读周期的读出周期与写周期的解码周期重叠。