公开(公告)号：US20050027901A1

公开(公告)日：2005-02-03

申请号：US10899196

申请日：2004-07-26

申请人： Moshe Simon ,  Erik Machnicki ,  Mark Longley

发明人： Moshe Simon ,  Erik Machnicki ,  Mark Longley

IPC分类号： G06F20060101 ,  G06F7/38 ,  G06F7/48 ,  G06F7/499 ,  G06F7/523 ,  G06F7/544 ,  G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F13/28

CPC分类号： G06F7/49921 ,  G06F7/49994 ,  G06F7/505 ,  G06F7/523 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F2207/382 ,  G06F2207/3828

摘要： A method and system for DMA transfer of data in scatter/gather mode. A table of buffer descriptors may be used to determine the next buffer to be used when a current buffer storing data that has been transferred or will be transferred and may be used in automatic buffer switching, which does not require processor intervention. Entries in the table of buffer descriptors are entered programmatically. The method and system also provide for hardware writing to table of packet descriptors which describes location and size of incoming data and can indicate whether a packet of data straddles two or more buffers, thus decoupling packet sizes from buffer sizes.

摘要翻译： 用于以分散/收集模式DMA传输数据的方法和系统。 可以使用缓冲器描述符表来确定当存储已被传送或将被传送的数据的当前缓冲器时使用的下一个缓冲器，并且可以用于不需要处理器干预的自动缓冲器切换。 缓冲区描述符表中的条目以编程方式输入。 该方法和系统还提供对描述入站数据的位置和大小的分组描述符的表的硬件写入，并且可以指示数据包是否跨越两个或更多个缓冲器，从而将分组大小与缓冲器大小分离。

公开(公告)号：US20050027969A1

公开(公告)日：2005-02-03

申请号：US10899193

申请日：2004-07-26

申请人： Moshe Simon ,  Erik Machnicki ,  David Harrison

发明人： Moshe Simon ,  Erik Machnicki ,  David Harrison

IPC分类号： G06F20060101 ,  G06F7/38 ,  G06F7/48 ,  G06F7/499 ,  G06F7/523 ,  G06F7/544 ,  G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F13/28

CPC分类号： G06F7/49921 ,  G06F7/49994 ,  G06F7/505 ,  G06F7/523 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F2207/382 ,  G06F2207/3828

摘要： Instructions for performing SIMD instructions, including parallel absolute value and parallel conditional move instructions, as well as a method and circuit for saturating results of operations. The parallel absolute value instruction determines the absolute value of operands based on the sign bit of the operands. When a parallel conditional move instruction is executed, status indicators corresponding to an operand are compared to a condition code in a register to determine whether the condition is true for any of the status indicators; if the condition is true, the corresponding operand is moved to a specified register. A method and circuit for handling saturation of a result of an operation are also provided. When two m-bit operands are added, as in an addition, average, or subtraction operation, if an average instruction is executed, the m most significant bits are output; otherwise, the m least significant bits are output and the result is saturated if there is overflow and saturation is enabled.

摘要翻译： 执行SIMD指令的指令，包括并行绝对值和并行条件移动指令，以及用于饱和运算结果的方法和电路。 并行绝对值指令根据操作数的符号位决定操作数的绝对值。 当执行并行条件移动指令时，将对应于操作数的状态指示符与寄存器中的条件代码进行比较，以确定任何状态指示符的条件是否为真; 如果条件为真，则将相应的操作数移动到指定的寄存器。 还提供了一种用于处理操作结果的饱和度的方法和电路。 当添加两个m位操作数时，如在加法，平均或减法操作中，如果执行平均指令，则输出m个最高有效位; 否则，输出m个最低有效位，并且如果有溢出和饱和使能，结果将饱和。

公开(公告)号：US20050235026A1

公开(公告)日：2005-10-20

申请号：US11153979

申请日：2005-06-16

申请人： Moshe Simon ,  Erik Machnicki ,  David Harrison ,  Rakesh Singh

发明人： Moshe Simon ,  Erik Machnicki ,  David Harrison ,  Rakesh Singh

IPC分类号： G06F20060101 ,  G06F7/38 ,  G06F7/48 ,  G06F7/499 ,  G06F7/523 ,  G06F7/544 ,  G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F13/28

CPC分类号： G06F7/49921 ,  G06F7/49994 ,  G06F7/505 ,  G06F7/523 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F2207/382 ,  G06F2207/3828

摘要： A multiply accumulate unit (“MAC”) that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation, each contain either four 8-bit operands, two 16-bit operands, or one 32-bit operand. Depending on the mode of operation, the MAC performs either sixteen 8×8 operations, four 16×16 operations, or one 32×32 operation. Results may be individually retrieved from registers and the corresponding accumulator cleared after the read cycle. In addition, the accumulators may be globally initialized. Two results from the 8×8 operations may be packed into a single 32-bit register. The MAC may also shift and saturate the products as required.

公开(公告)号：US20050027773A1

公开(公告)日：2005-02-03

申请号：US10775461

申请日：2004-02-09

申请人： Erik Machnicki ,  David Harrison ,  Rakesh Singh

发明人： Erik Machnicki ,  David Harrison ,  Rakesh Singh

IPC分类号： G06F20060101 ,  G06F7/38 ,  G06F7/48 ,  G06F7/499 ,  G06F7/523 ,  G06F7/544 ,  G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F13/28

CPC分类号： G06F7/49921 ,  G06F7/49994 ,  G06F7/505 ,  G06F7/523 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F2207/382 ,  G06F2207/3828

摘要： A multiply accumulate unit (“MAC”) that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation, each contain either four 8-bit operands, two 16-bit operands, or one 32-bit operand. Depending on the mode of operation, the MAC performs either sixteen 8×8 operations, four 16×16 operations, or one 32×32 operation. Results may be individually retrieved from registers and the corresponding accumulator cleared after the read cycle. In addition, the accumulators may be globally initialized. Two results from the 8×8 operations may be packed into a single 32-bit register. The MAC may also shift and saturate the products as required.

摘要翻译： 对打包的整数数据执行操作的乘法累加单元（“MAC”）。 在一个实施例中，MAC接收2个32位数据字，其取决于指定的操作模式，每个包含四个8位操作数，两个16位操作数或一个32位操作数。 根据操作模式，MAC执行十六个8x8操作，四个16x16操作或一个32x32操作。 结果可以从寄存器单独检索，相应的累加器在读周期后清零。 此外，累加器可以被全局初始化。 来自8x8操作的两个结果可以打包到一个32位寄存器中。 MAC也可能会根据需要移动和饱和产品。

公开(公告)号：US09081517B2

公开(公告)日：2015-07-14

申请号：US13223282

申请日：2011-08-31

申请人： Kleanthes Koniaris ,  Josh P. de Cesare ,  Timothy J. Millet ,  Jung Wook Cho ,  Erik Machnicki

发明人： Kleanthes Koniaris ,  Josh P. de Cesare ,  Timothy J. Millet ,  Jung Wook Cho ,  Erik Machnicki

IPC分类号： G06F1/32 ,  G06F1/10 ,  G06F1/24

CPC分类号： G06F1/10 ,  G06F1/24 ,  G06F1/3237 ,  Y02D10/128

摘要： A system and method for automatically updating with hardware clock tree settings on a system-on-a-chip (SOC). A SOC includes a hardware clock control unit (HCCU) coupled to a software interface and a clock tree. The SOC also includes multiple integrated circuit (IC) devices, wherein each IC device receives one or more associated core clocks provided by one or more phase lock loops (PLLs) via the clock tree. The HCCU receives a software-initiated request specifying a given IC device is to be enabled. The HCCU identifies one or more core clocks used by the given IC device. For each one of the identified core clocks, the HCCU configures associated circuitry within the clock tree to generate an identified core clock. The HCCU may also traverse the clock tree and disable clock generating gates found not to drive any other enabled gates or IC devices.

摘要翻译： 一种使用片上系统（SOC）上的硬件时钟树设置自动更新的系统和方法。 SOC包括耦合到软件接口和时钟树的硬件时钟控制单元（HCCU）。 SOC还包括多个集成电路（IC）器件，其中每个IC器件经由时钟树接收由一个或多个锁相环（PLL）提供的一个或多个相关核心时钟。 HCCU接收软件发起的请求，指定要启用给定的IC设备。 HCCU识别给定IC器件使用的一个或多个核心时钟。 对于每个识别的核心时钟，HCCU配置时钟树内的相关电路以产生识别的核心时钟。 HCCU还可以遍历时钟树，并禁用发现不驱动任何其他启用的门或IC设备的时钟生成门。