公开(公告)号：US08044498B2

公开(公告)日：2011-10-25

申请号：US12164503

申请日：2008-06-30

Applicant: Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

Inventor： Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

IPC: H01L23/07

CPC classification number: H01L25/0657 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012

Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on.Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.

Abstract translation: 可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。 使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。 提供给半导体芯片安装的密封子板的突起附接到封装基板。 多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。

公开(公告)号：US20090065922A1

公开(公告)日：2009-03-12

申请号：US12235734

申请日：2008-09-23

Applicant: Moriyoshi NAKASHIMA ,  Kazuo Kobayashi ,  Natsuo Ajika

Inventor： Moriyoshi NAKASHIMA ,  Kazuo Kobayashi ,  Natsuo Ajika

IPC: H01L23/02

CPC classification number: H01L23/3135 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11′). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.

Abstract translation: 半导体芯片安装插入件（60）通过在半导体芯片（50）和插入件（20）之间执行引线键合而构成，其中连接到芯片（50）的端子（51）的端子（21）和分离的端子 （22）形成在插入件（20）的上表面上。 半导体芯片（30）安装在封装基板（10）的顶面上，插入件（60）粘接到芯片（30）的上部，并且在端子（22）和 端子（11'）。 当以这种方式配置具有组合成一个封装的多个半导体芯片的半导体器件时，可以容易地保证每个半导体芯片的KGD（Known-Good-Die），并且可以以高产量的良好单元制造半导体器件。 此外，半导体芯片可以原样使用，而不限制其端子的位置，间距，信号布置等。

公开(公告)号：US20080265433A1

公开(公告)日：2008-10-30

申请号：US12164503

申请日：2008-06-30

Applicant: Moriyoshi NAKASHIMA ,  Kazuo Kobayashi ,  Natsuo Ajika

Inventor： Moriyoshi NAKASHIMA ,  Kazuo Kobayashi ,  Natsuo Ajika

IPC: H01L23/49

CPC classification number: H01L25/0657 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012

Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on.Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.

公开(公告)号：US07420206B2

公开(公告)日：2008-09-02

申请号：US11456913

申请日：2006-07-12

Applicant: Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

Inventor： Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

IPC: H01L29/10

CPC classification number: H01L25/0657 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012

Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.

Abstract translation: 可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。 使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。 提供给半导体芯片安装的密封子板的突起附接到封装基板。 多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。

公开(公告)号：US20080121878A1

公开(公告)日：2008-05-29

申请号：US11456913

申请日：2006-07-12

Applicant: Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

Inventor： Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

IPC: H01L23/58 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012

Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on.Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.

Abstract translation: 可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。 使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。 提供给半导体芯片安装的密封子板的突起附接到封装基板。 多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。

公开(公告)号：US20110074045A2

公开(公告)日：2011-03-31

申请号：US12164503

申请日：2008-06-30

Applicant: Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

Inventor： Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

IPC: H01L23/49

CPC classification number: H01L25/0657 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012

Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.

Abstract translation: 可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。 使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。 提供给半导体芯片安装的密封子板的突起附接到封装基板。 多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。

公开(公告)号：US07723835B2

公开(公告)日：2010-05-25

申请号：US12235734

申请日：2008-09-23

Applicant: Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

Inventor： Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

IPC: H01L23/02

CPC classification number: H01L23/3135 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11′). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.

Abstract translation: 半导体芯片安装插入件（60）通过在半导体芯片（50）和插入件（20）之间执行引线键合而构成，其中连接到芯片（50）的端子（51）的端子（21）和分离的端子 （22）形成在插入件（20）的上表面上。 半导体芯片（30）安装在封装基板（10）的顶面上，插入件（60）粘接到芯片（30）的上部，并且在端子（22）和 端子（11'）。 当以这种方式配置具有组合成一个封装的多个半导体芯片的半导体器件时，可以容易地保证每个半导体芯片的KGD（Known-Good-Die），并且可以以高产量的良好单元制造半导体器件。 此外，半导体芯片可以原样使用，而不限制其端子的位置，间距，信号布置等。

公开(公告)号：US20070132080A1

公开(公告)日：2007-06-14

申请号：US10595424

申请日：2003-12-15

Applicant: Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

Inventor： Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

IPC: H01L23/02

CPC classification number: H01L23/3135 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11′). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.

Abstract translation: 半导体芯片安装插入件（60）通过在半导体芯片（50）和插入件（20）之间执行引线键合而构成，其中连接到芯片（50）的端子（51）的端子（21）和分离的端子 （22）形成在插入件（20）的上表面上。 半导体芯片（30）安装在封装基板（10）的顶面上，插入件（60）粘接到芯片（30）的上部，并且在端子（22）和 端子（11'）。 当以这种方式配置具有组合成一个封装的多个半导体芯片的半导体器件时，可以容易地保证每个半导体芯片的KGD（Known-Good-Die），并且可以以高产量的良好单元制造半导体器件。 此外，半导体芯片可以原样使用，而不限制其端子的位置，间距，信号布置等。

公开(公告)号：US08404601B2

公开(公告)日：2013-03-26

申请号：US13494418

申请日：2012-06-12

Applicant: Kazuo Kobayashi

Inventor： Kazuo Kobayashi

IPC: H01L21/31

Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of: (a) introducing hydrogen and oxygen on a SiC substrate; and (b) subjecting the hydrogen and the oxygen to a combustion reaction on the SiC substrate to form a gate oxide film being a silicon oxide film on a surface of the SiC substrate by the combustion reaction.

公开(公告)号：US20120081475A1

公开(公告)日：2012-04-05

申请号：US13231216

申请日：2011-09-13

Applicant: Koichiro HARA ,  Kazuo Kobayashi

Inventor： Koichiro HARA ,  Kazuo Kobayashi

IPC: B41J2/045 ,  B41J2/16

CPC classification number: B41J2/14233

Abstract: There is provided a liquid discharging head discharging a liquid, including: a channel unit having a liquid channel including a pressure chamber which has an opening at one surface of the channel unit; a piezoelectric element formed of a piezoelectric material; an intermediate member preventing the liquid in the pressure chamber and the piezoelectric element from making contact with each other; a first adhesive layer composed of a first adhesive and adhering the channel unit and the intermediate member, the first adhesive being a thermo-setting adhesive starting to be cured at a first temperature; and a second adhesive layer composed of a second adhesive and adhering the intermediate member and the piezoelectric element, the second adhesive starting to be cured at a second temperature lower than the first temperature.

Abstract translation: 提供了一种排出液体的液体排放头，包括：通道单元，其具有液体通道，该液体通道包括在通道单元的一个表面上具有开口的压力室; 由压电材料形成的压电元件; 防止压力室中的液体和压电元件彼此接触的中间构件; 第一粘合剂层，由第一粘合剂组成并粘合通道单元和中间构件，第一粘合剂是开始在第一温度下固化的热固性粘合剂; 以及第二粘合剂层，由第二粘合剂组成并粘合所述中间构件和所述压电元件，所述第二粘合剂在比所述第一温度低的第二温度下开始固化。