Invention Grant
- Patent Title: Semiconductor device package structure
- Patent Title (中): 半导体器件封装结构
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Application No.: US12235734Application Date: 2008-09-23
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Publication No.: US07723835B2Publication Date: 2010-05-25
- Inventor: Moriyoshi Nakashima , Kazuo Kobayashi , Natsuo Ajika
- Applicant: Moriyoshi Nakashima , Kazuo Kobayashi , Natsuo Ajika
- Applicant Address: JP Hyogo
- Assignee: GENUSION, Inc.
- Current Assignee: GENUSION, Inc.
- Current Assignee Address: JP Hyogo
- Agency: Renner, Otto, Boisselle & Sklar, LLP
- Priority: JP2003-359896 20031020
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11′). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.
Public/Granted literature
- US20090065922A1 SEMICONDUCTOR DEVICE PACKAGE STRUCTURE Public/Granted day:2009-03-12
Information query
IPC分类: