公开(公告)号：US20140083979A1

公开(公告)日：2014-03-27

申请号：US14116952

申请日：2012-05-10

Applicant: Shigeru Tahara ,  Eiichi Nishimura ,  Hiroshi Tomita ,  Tokuhisa Ohiwa ,  Hisashi Okuchi ,  Mitsuhiro Omura

Inventor： Shigeru Tahara ,  Eiichi Nishimura ,  Hiroshi Tomita ,  Tokuhisa Ohiwa ,  Hisashi Okuchi ,  Mitsuhiro Omura

IPC: B05D3/14

CPC classification number: B05D3/145 ,  H01L21/02057 ,  H01L21/02063 ,  H01L21/31116

Abstract: A deposit removal method for removing deposits deposited on the surface of a pattern formed on a substrate by etching, includes an oxygen plasma treatment process for exposing the substrate to oxygen plasma while heating the substrate and a cycle treatment process for, after the oxygen plasma treatment process, repeating multiple cycles of a first period and a second period. In the first period, the substrate is exposed to a mixture of hydrogen fluoride gas and alcohol gas inside a processing chamber and the partial pressure of the alcohol gas is set to the first partial pressure. In the second period, the partial pressure of the alcohol gas is set to the second partial pressure lower than the first partial pressure by exhausting the inside of the processing chamber.

Abstract translation: 通过蚀刻去除沉积在形成在基板上的图案的表面上的沉积物的沉积物去除方法包括用于在加热基板的同时将基板暴露于氧等离子体的氧等离子体处理工艺和在氧等离子体处理之后的循环处理 处理，重复第一周期和第二周期的多个周期。 在第一阶段中，将基板暴露于处理室内的氟化氢气体和醇气体的混合物，并将醇气体的分压设定为第一分压。 在第二时段，通过排出处理室的内部，将醇气体的分压设定为低于第一分压的第二分压。

公开(公告)号：US08198669B2

公开(公告)日：2012-06-12

申请号：US12615120

申请日：2009-11-09

Applicant: Mitsuhiro Omura

Inventor： Mitsuhiro Omura

IPC: H01L29/792

CPC classification number: H01L27/11578 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device includes: a first layer; a second layer; a columnar structural unit; and a side portion. The second layer is provided on a major surface of the first layer. The columnar structural unit is conductive and aligned in the first layer and the second layer to pass through the major surface. The side portion is added to a side wall of the columnar structural unit on the second layer side of the major surface.

Abstract translation: 半导体器件包括：第一层; 第二层; 柱状结构单元; 和侧部。 第二层设置在第一层的主表面上。 柱状结构单元是导电的并且在第一层和第二层中对准以通过主表面。 侧面部分被添加到主表面的第二层侧上的柱状结构单元的侧壁。

公开(公告)号：US20110097888A1

公开(公告)日：2011-04-28

申请号：US12929125

申请日：2011-01-03

Applicant: Mitsuhiro Omura ,  Satoshi Nagashima ,  Katsunori Yahashi ,  Jungo Inaba ,  Daina Inoue

Inventor： Mitsuhiro Omura ,  Satoshi Nagashima ,  Katsunori Yahashi ,  Jungo Inaba ,  Daina Inoue

IPC: H01L21/28

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

Abstract translation: 半导体存储器件包括具有层叠栅结构的多个晶体管。 每个晶体管包括半导体衬底，形成在半导体衬底上的栅极绝缘体，形成在半导体衬底上的栅极绝缘体插入的下栅极，形成在下栅极上的栅极绝缘体和在下栅极上形成并硅化的上栅极 间隔绝缘体插入。 晶体管的一部分具有通过栅极间绝缘体形成的孔，以将下栅极与上栅极连接，并且还包括由绝缘体构成并形成为小于上栅极且大于上栅极上方的孔的阻挡膜以覆盖 光圈。

公开(公告)号：US07232763B2

公开(公告)日：2007-06-19

申请号：US10959501

申请日：2004-10-07

Applicant: Mitsuhiro Omura ,  Makiko Katano ,  Shoko Ito ,  Takaya Matsushita ,  Hisashi Kaneko

Inventor： Mitsuhiro Omura ,  Makiko Katano ,  Shoko Ito ,  Takaya Matsushita ,  Hisashi Kaneko

IPC: H01L21/311

CPC classification number: H01L21/76838 ,  H01L21/02046 ,  H01L21/31116

Abstract: A method of manufacturing a semiconductor device includes subjecting a semiconductor wafer, which includes a copper layer formed above a semiconductor substrate and covered with an insulating film, to a dry etching using a fluorocarbon gas to partially remove the insulating film, thereby at least partially exposing a surface of the copper layer. The copper layer, the surface of which is at least partially exposed is subjected to a nitrogen plasma treatment. The semiconductor wafer having the nitrogen plasma-treated copper layer is exposed to atmosphere, and then the semiconductor wafer is subjected to a surface treatment.

Abstract translation: 一种制造半导体器件的方法包括使用碳氟化合物气体对包含形成在半导体衬底之上并被绝缘膜形成的铜层的半导体晶片进行干蚀刻，以部分地去除绝缘膜，从而至少部分曝光 铜层的表面。 将其表面至少部分暴露的铜层进行氮等离子体处理。 将具有氮等离子体处理的铜层的半导体晶片暴露于大气中，然后对半导体晶片进行表面处理。

公开(公告)号：US09126229B2

公开(公告)日：2015-09-08

申请号：US14116952

申请日：2012-05-10

Applicant: Shigeru Tahara ,  Eiichi Nishimura ,  Hiroshi Tomita ,  Tokuhisa Ohiwa ,  Hisashi Okuchi ,  Mitsuhiro Omura

Inventor： Shigeru Tahara ,  Eiichi Nishimura ,  Hiroshi Tomita ,  Tokuhisa Ohiwa ,  Hisashi Okuchi ,  Mitsuhiro Omura

IPC: B05D3/14 ,  H01L21/02 ,  H01L21/311

CPC classification number: B05D3/145 ,  H01L21/02057 ,  H01L21/02063 ,  H01L21/31116

Abstract: A deposit removal method for removing deposits deposited on the surface of a pattern formed on a substrate by etching, includes an oxygen plasma treatment process for exposing the substrate to oxygen plasma while heating the substrate and a cycle treatment process for, after the oxygen plasma treatment process, repeating multiple cycles of a first period and a second period. In the first period, the substrate is exposed to a mixture of hydrogen fluoride gas and alcohol gas inside a processing chamber and the partial pressure of the alcohol gas is set to the first partial pressure. In the second period, the partial pressure of the alcohol gas is set to the second partial pressure lower than the first partial pressure by exhausting the inside of the processing chamber.

Abstract translation: 通过蚀刻去除沉积在形成在基板上的图案的表面上的沉积物的沉积物去除方法包括用于在加热基板的同时将基板暴露于氧等离子体的氧等离子体处理工艺和在氧等离子体处理之后的循环处理 处理，重复第一周期和第二周期的多个周期。 在第一阶段中，将基板暴露于处理室内的氟化氢气体和醇气体的混合物，并将醇气体的分压设定为第一分压。 在第二时段，通过排出处理室的内部，将醇气体的分压设定为低于第一分压的第二分压。

公开(公告)号：US08460997B2

公开(公告)日：2013-06-11

申请号：US12929125

申请日：2011-01-03

Applicant: Mitsuhiro Omura ,  Satoshi Nagashima ,  Katsunori Yahashi ,  Jungo Inaba ,  Daina Inoue

Inventor： Mitsuhiro Omura ,  Satoshi Nagashima ,  Katsunori Yahashi ,  Jungo Inaba ,  Daina Inoue

IPC: H01L21/302

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

Abstract translation: 半导体存储器件包括具有层叠栅结构的多个晶体管。 每个晶体管包括半导体衬底，形成在半导体衬底上的栅极绝缘体，形成在半导体衬底上的栅极绝缘体插入的下栅极，形成在下栅极上的栅极绝缘体和在下栅极上形成并硅化的上栅极 间隔绝缘体插入。 晶体管的一部分具有通过栅极间绝缘体形成的孔，以将下栅极与上栅极连接，并且还包括由绝缘体构成并形成为小于上栅极且大于上栅极上方的孔的阻挡膜以覆盖 光圈。

公开(公告)号：US20120315758A1

公开(公告)日：2012-12-13

申请号：US13426513

申请日：2012-03-21

Applicant: Noriko SAKURAI ,  Mitsuhiro Omura ,  Toshiyuki Sasaki ,  Itsuko Sakai

Inventor： Noriko SAKURAI ,  Mitsuhiro Omura ,  Toshiyuki Sasaki ,  Itsuko Sakai

IPC: H01L21/768 ,  H01L21/3065

CPC classification number: H01L21/3065 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor device manufacturing method comprises mounting a supporting substrate on a front surface side of a silicon substrate having an interconnection layer and function elements formed on a front surface side, polishing a back surface side of the silicon substrate, forming a mask having an opening and an opening for a dummy hole having a diameter smaller than that of the above opening on the back surface side of the silicon substrate, etching portions exposed to the openings of the mask from the back surface side of the silicon substrate to form a via hole that reaches a part of the interconnection layer and form a dummy hole to an intermediate portion of the silicon substrate, and forming an interconnection material in the via hole.

Abstract translation: 根据一个实施例，一种半导体器件制造方法包括将支撑衬底安装在具有互连层的硅衬底的前表面侧上，并且在前表面侧形成功能元件，抛光硅衬底的背面侧，形成 掩模，其具有开口和用于在硅衬底的背面侧具有比上述开口的直径小的虚拟孔的开口，从硅衬底的背面侧暴露于掩模的开口的蚀刻部分到 形成通孔，其到达所述互连层的一部分并且形成到所述硅衬底的中间部分的虚拟孔，并且在所述通孔中形成互连材料。

公开(公告)号：US07906434B2

公开(公告)日：2011-03-15

申请号：US12539937

申请日：2009-08-12

Applicant: Junichi Hashimoto ,  Mitsuhiro Omura ,  Yasuyoshi Hyodo ,  Takamichi Tsuchiya

Inventor： Junichi Hashimoto ,  Mitsuhiro Omura ,  Yasuyoshi Hyodo ,  Takamichi Tsuchiya

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/76816

Abstract: A semiconductor device manufacturing method includes: depositing a first insulating film and a second insulating film on a substrate sequentially and forming a pattern on the second insulating film; forming a silicon film on the pattern; forming a sidewall made of the silicon film by processing the silicon film until a part of the second insulating film is exposed by use of etch-back; removing the second insulating film; and performing dry etching by use of a fluorocarbon-based gas, to process the first insulating film by using the sidewall as a mask. The processing of the first insulating film includes applying on the substrate a self-bias voltage Vdc that satisfies a relational expression of Vdc

Abstract translation: 一种半导体器件制造方法，包括：依次在基板上沉积第一绝缘膜和第二绝缘膜，并在第二绝缘膜上形成图案; 在图案上形成硅膜; 通过处理硅膜形成由硅膜制成的侧壁，直到通过使用回蚀来露出第二绝缘膜的一部分; 去除第二绝缘膜; 并使用氟碳系气体进行干法蚀刻，使用侧壁作为掩模来处理第一绝缘膜。 第一绝缘膜的处理包括在衬底上施加满足Vdc <46x-890的关系式的自偏压Vdc，其中构成侧壁的硅膜的膜厚为xnm（19.5≤n1E; x＆ ; 22.1）。

公开(公告)号：US20050106866A1

公开(公告)日：2005-05-19

申请号：US10959501

申请日：2004-10-07

Applicant: Mitsuhiro Omura ,  Makiko Katano ,  Shoko Ito ,  Takaya Matsushita ,  Hisashi Kaneko

Inventor： Mitsuhiro Omura ,  Makiko Katano ,  Shoko Ito ,  Takaya Matsushita ,  Hisashi Kaneko

IPC: H01L21/00 ,  H01L21/26 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/324 ,  H01L21/44 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76838 ,  H01L21/02046 ,  H01L21/31116

Abstract: A method of manufacturing a semiconductor device includes subjecting a semiconductor wafer, which includes a copper layer formed above a semiconductor substrate and covered with an insulating film, to a dry etching using a fluorocarbon gas to partially remove the insulating film, thereby at least partially exposing a surface of the copper layer. The copper layer, the surface of which is at least partially exposed is subjected to a nitrogen plasma treatment. The semiconductor wafer having the nitrogen plasma-treated copper layer is exposed to atmosphere, and then the semiconductor wafer is subjected to a surface treatment.

Abstract translation: 一种制造半导体器件的方法包括使用碳氟化合物气体对包含形成在半导体衬底之上并被绝缘膜形成的铜层的半导体晶片进行干蚀刻，以部分地去除绝缘膜，从而至少部分曝光 铜层的表面。 将其表面至少部分暴露的铜层进行氮等离子体处理。 将具有氮等离子体处理的铜层的半导体晶片暴露于大气中，然后对半导体晶片进行表面处理。

公开(公告)号：US06835999B2

公开(公告)日：2004-12-28

申请号：US10458267

申请日：2003-06-11

Applicant: Mitsuhiro Omura ,  Fumio Sato

Inventor： Mitsuhiro Omura ,  Fumio Sato

IPC: H01L2900

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a first metal wiring and a fuse, both being formed as the same level above the semiconductor substrate, a first insulating film formed on the first metal wiring and the fuse, the first insulating film having a first pad opening arriving at the first metal wiring, a second metal wiring formed at least within the first pad opening, the second metal wiring not extending above the fuse, a stopper film formed on the first insulating film and the second metal wiring, and a second insulating film formed above the stopper film. A second pad opening is formed to expose the second metal wiring by removing the second insulating film and the stopper film, a fuse opening is formed above at least the fuse by removing the second insulating film and the stopper film, and by removing the first insulating film incompletely.