公开(公告)号：US08563977B2

公开(公告)日：2013-10-22

申请号：US12672103

申请日：2008-09-18

Applicant: Mikio Shimada ,  Ryo Hayashi ,  Hideya Kumomi

Inventor： Mikio Shimada ,  Ryo Hayashi ,  Hideya Kumomi

IPC: H01L33/16 ,  H01L33/00

CPC classification number: H01L33/16 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696 ,  H01L33/0054

Abstract: A transistor is constituted of a gate electrode 2, a gate insulation layer 3, a semiconductor layer 4 formed of an amorphous oxide, a source electrode 5, a drain electrode 6 and a protective layer 7. The protective layer 7 is provided on the semiconductor layer 4 in contact with the semiconductor layer 4, and the semiconductor layer 4 includes a first layer at least functioning as a channel layer and a second layer having higher resistance than the first layer. The first layer is provided on the gate electrode 2 side of the semiconductor layer 4 and the second layer is provided on the protective layer 7 side of the semiconductor layer 4.

Abstract translation: 晶体管由栅电极2，栅绝缘层3，由非晶氧化物形成的半导体层4，源电极5，漏电极6和保护层7构成。保护层7设置在半导体 层4与半导体层4接触，并且半导体层4包括至少用作沟道层的第一层和具有比第一层更高的电阻的第二层。 第一层设置在半导体层4的栅电极2侧，第二层设置在半导体层4的保护层7侧。

公开(公告)号：US20100213459A1

公开(公告)日：2010-08-26

申请号：US12672103

申请日：2008-09-18

Applicant: Mikio Shimada ,  Ryo Hayashi ,  Hideya Kumomi

Inventor： Mikio Shimada ,  Ryo Hayashi ,  Hideya Kumomi

IPC: H01L29/786 ,  H01L21/44

CPC classification number: H01L33/16 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696 ,  H01L33/0054

Abstract: A transistor is constituted of a gate electrode 2, a gate insulation layer 3, a semiconductor layer 4 formed of an amorphous oxide, a source electrode 5, a drain electrode 6 and a protective layer 7. The protective layer 7 is provided on the semiconductor layer 4 in contact with the semiconductor layer 4, and the semiconductor layer 4 includes a first layer at least functioning as a channel layer and a second layer having higher resistance than the first layer. The first layer is provided on the gate electrode 2 side of the semiconductor layer 4 and the second layer is provided on the protective layer 7 side of the semiconductor layer 4.

Abstract translation: 晶体管由栅电极2，栅绝缘层3，由非晶氧化物形成的半导体层4，源电极5，漏电极6和保护层7构成。保护层7设置在半导体 层4与半导体层4接触，并且半导体层4包括至少用作沟道层的第一层和具有比第一层更高的电阻的第二层。 第一层设置在半导体层4的栅电极2侧，第二层设置在半导体层4的保护层7侧。

公开(公告)号：US20120132911A1

公开(公告)日：2012-05-31

申请号：US13369406

申请日：2012-02-09

Applicant: Mikio Shimada ,  Ryo Hayashi ,  Hideya Kumomi

Inventor： Mikio Shimada ,  Ryo Hayashi ,  Hideya Kumomi

IPC: H01L29/786

CPC classification number: H01L33/16 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696 ,  H01L33/0054

Abstract: A transistor is constituted of a gate electrode 2, a gate insulation layer 3, a semiconductor layer 4 formed of an amorphous oxide, a source electrode 5, a drain electrode 6 and a protective layer 7. The protective layer 7 is provided on the semiconductor layer 4 in contact with the semiconductor layer 4, and the semiconductor layer 4 includes a first layer at least functioning as a channel layer and a second layer having higher resistance than the first layer. The first layer is provided on the gate electrode 2 side of the semiconductor layer 4 and the second layer is provided on the protective layer 7 side of the semiconductor layer 4.

Abstract translation: 晶体管由栅电极2，栅绝缘层3，由非晶氧化物形成的半导体层4，源电极5，漏电极6和保护层7构成。保护层7设置在半导体 层4与半导体层4接触，并且半导体层4包括至少用作沟道层的第一层和具有比第一层更高的电阻的第二层。 第一层设置在半导体层4的栅电极2侧，第二层设置在半导体层4的保护层7侧。

公开(公告)号：US08624240B2

公开(公告)日：2014-01-07

申请号：US13188215

申请日：2011-07-21

Applicant: Ayumu Sato ,  Hideya Kumomi ,  Hisato Yabuta ,  Ryo Hayashi ,  Yasuyoshi Takai

Inventor： Ayumu Sato ,  Hideya Kumomi ,  Hisato Yabuta ,  Ryo Hayashi ,  Yasuyoshi Takai

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78648

Abstract: Provided is a top gate thin film transistor, including on a substrate: a source electrode layer; a drain electrode layer; an oxide semiconductor layer; a gate insulating layer; a gate electrode layer including an amorphous oxide semiconductor containing at least one kind of element selected from among In, Ga, Zn, and Sn; and a protective layer containing hydrogen, in which: the gate insulating layer is formed on a channel region of the oxide semiconductor layer; the gate electrode layer is formed on the gate insulating layer; and the protective layer is formed on the gate electrode layer.

Abstract translation: 提供了一种顶栅薄膜晶体管，其包括在基板上：源电极层; 漏电极层; 氧化物半导体层; 栅极绝缘层; 包含含有选自In，Ga，Zn和Sn中的至少一种元素的非晶氧化物半导体的栅极电极层; 以及含有氢的保护层，其中：所述栅绝缘层形成在所述氧化物半导体层的沟道区上; 栅电极层形成在栅极绝缘层上; 并且在栅电极层上形成保护层。

公开(公告)号：US08599111B2

公开(公告)日：2013-12-03

申请号：US12162929

申请日：2007-03-08

Applicant: Katsumi Abe ,  Masafumi Sano ,  Ryo Hayashi ,  Hideya Kumomi

Inventor： Katsumi Abe ,  Masafumi Sano ,  Ryo Hayashi ,  Hideya Kumomi

IPC: G09G3/30 ,  G09G5/10

CPC classification number: G09G3/3283 ,  G09G3/2014 ,  G09G3/325 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2310/066 ,  G09G2320/0238 ,  G09G2320/043

Abstract: A driving circuit of a display element includes a current source circuit having a first transistor and a holding circuit for holding a gate voltage of the first transistor during a first period at an electric potential corresponding to a constant current to be supplied to the display element, and a control circuit including a second transistor connected in series to the current source circuit and connected in parallel to the display element and the capacitor element whose one terminal is connected to a gate of the second transistor and the other terminal is connected to a line, and controlling the light emission time of the display element by controlling the second transistor during a third period. A constant voltage is applied from the line during the first period. The gray-scale voltage is applied from the line during a second period, and the gate of the second transistor and the one terminal are short-circuited. In addition, an electric charge based on the difference between the gray-scale voltage and the gate voltage of the second transistor is accumulated in the capacitor element, and a sweep voltage is applied during the third period, so that the ON time of the second transistor is controlled.

Abstract translation: 显示元件的驱动电路包括具有第一晶体管和保持电路的电流源电路，所述保持电路用于在第一周期期间保持与要提供给显示元件的恒定电流相对应的电位的第一晶体管的栅极电压， 以及控制电路，包括与所述电流源电路串联连接并并联连接到所述显示元件的第二晶体管和所述电容器元件，所述电容器元件的一个端子连接到所述第二晶体管的栅极，并且所述另一端子连接到线路， 以及通过在第三周期期间控制所述第二晶体管来控制所述显示元件的发光时间。 在第一周期期间从线路施加恒定电压。 在第二周期期间，从线路施加灰度电压，并且第二晶体管的栅极和一个端子短路。 此外，基于第二晶体管的灰度电压和栅极电压之间的差异的电荷累积在电容器元件中，并且在第三周期期间施加扫描电压，使得第二时间的导通时间 晶体管被控制。

公开(公告)号：US08592815B2

公开(公告)日：2013-11-26

申请号：US13001000

申请日：2009-06-30

Applicant: Yoshinori Tateishi ,  Masato Ofuji ,  Hideya Kumomi ,  Ryo Hayashi

Inventor： Yoshinori Tateishi ,  Masato Ofuji ,  Hideya Kumomi ,  Ryo Hayashi

IPC: H01L29/04 ,  H01L21/00

CPC classification number: H01L27/3248 ,  H01L27/12 ,  H01L27/3258 ,  H01L27/3272 ,  H01L29/24 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78693

Abstract: There is provided a light emitting display apparatus including at least a light emitting element and a thin film transistor (TFT) for driving the light emitting element, characterized in that a mechanism is provided in which a semiconductor constituting the TFT is irradiated with at least a part of light whose wavelength is longer than a predetermined wavelength among the light emitted by the light emitting element.

公开(公告)号：US08525175B2

公开(公告)日：2013-09-03

申请号：US13161328

申请日：2011-06-15

Applicant: Sho Suzuki ,  Katsumi Abe ,  Ryo Hayashi ,  Hideya Kumomi

Inventor： Sho Suzuki ,  Katsumi Abe ,  Ryo Hayashi ,  Hideya Kumomi

IPC: H01L29/04

CPC classification number: H01L27/1225 ,  H01L27/124

Abstract: An electronic device includes: multiple electronic elements each including a semiconductor film; and an element isolation region provided between adjacent ones of the multiple electronic elements, the element isolation region including a semiconductor film having a bandgap of 1.95 eV or more, an insulating film, and an element isolation electrode, the element isolation electrode being an electrode which is separated from the semiconductor film of the element isolation region by the insulating film and is applied with a voltage so as to increase a resistance of the semiconductor film of the element isolation region, to thereby electrically isolate the multiple electronic elements from one another.

Abstract translation: 电子设备包括：多个电子元件，每个电子元件包括半导体膜; 以及设置在所述多个电子元件的相邻元件之间的元件隔离区域，所述元件隔离区域包括具有1.95eV以上的带隙的半导体膜，绝缘膜和元件隔离电极，所述元件隔离电极为电极， 通过绝缘膜与元件隔离区域的半导体膜分离，并施加电压以增加元件隔离区域的半导体膜的电阻，从而使多个电子元件彼此电隔离。

公开(公告)号：US20130214854A1

公开(公告)日：2013-08-22

申请号：US13881266

申请日：2011-10-31

Applicant: Katsumi Abe ,  Hideya Kumomi ,  Ryo Hayashi ,  Tatsuya Iwasaki

Inventor： Katsumi Abe ,  Hideya Kumomi ,  Ryo Hayashi ,  Tatsuya Iwasaki

IPC: H01L29/786 ,  G05F3/02

CPC classification number: H01L29/7869 ,  G05F3/02 ,  H01L27/0705 ,  H01L27/11807 ,  H01L27/1203 ,  H03K17/063 ,  H03K17/693 ,  H03K19/20

Abstract: Provided is a semiconductor device, including an electrode, a first insulator, a first semiconductor having a bandgap of 2 eV or greater, a second insulator, and a second semiconductor, which are stacked on one another, and at least further including one or more electrodes in contact with the first semiconductor and two or more electrodes in contact with the second semiconductor.

Abstract translation: 提供了一种半导体器件，其包括彼此堆叠的电极，第一绝缘体，具有2eV以上的带隙的第一半导体，第二绝缘体和第二半导体，并且至少进一步包括一个或多个 与第一半导体接触的电极和与第二半导体接触的两个或多个电极。

公开(公告)号：US08084331B2

公开(公告)日：2011-12-27

申请号：US12865032

申请日：2009-03-02

Applicant: Masato Ofuji ,  Katsumi Abe ,  Hisae Shimizu ,  Ryo Hayashi ,  Masafumi Sano ,  Hideya Kumomi ,  Yasuyoshi Takai ,  Takehiko Kawasaki ,  Norio Kaneko

Inventor： Masato Ofuji ,  Katsumi Abe ,  Hisae Shimizu ,  Ryo Hayashi ,  Masafumi Sano ,  Hideya Kumomi ,  Yasuyoshi Takai ,  Takehiko Kawasaki ,  Norio Kaneko

IPC: H01L21/331

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L29/78633

Abstract: In a method of treating a semiconductor element which at least includes a semiconductor, a threshold voltage of the semiconductor element is changed by irradiating the semiconductor with light with a wavelength longer than an absorption edge wavelength of the semiconductor. The areal density of in-gap states in the semiconductor is 1013 cm−2eV−1 or less. The band gap may be 2 eV or greater. The semiconductor may include at least one selected from the group consisting of In, Ga, Zn and Sn. The semiconductor may be one selected from the group consisting of amorphous In—Ga—Zn—O (IGZO), amorphous In—Zn—O (IZO) and amorphous Zn—Sn—O (ZTO). The light irradiation may induce the threshold voltage shift in the semiconductor element, the shift being of the opposite sign to the threshold voltage shift caused by manufacturing process history, time-dependent change, electrical stress or thermal stress.

Abstract translation: 在处理至少包括半导体的半导体元件的方法中，通过用比半导体的吸收边缘波长更长的光照射半导体来改变半导体元件的阈值电压。 半导体中间隙状态的面密度为1013cm-2eV-1或更小。 带隙可以是2eV或更大。 半导体可以包括选自In，Ga，Zn和Sn中的至少一种。 半导体可以是选自由无定形In-Ga-Zn-O（IGZO），非晶In-Zn-O（IZO）和无定形Zn-Sn-O（ZTO）组成的组中的一种。 光照射可以引起半导体元件中的阈值电压偏移，该偏移与由制造工艺历史，时间依赖变化，电应力或热应力引起的阈值电压偏移相反。

公开(公告)号：US20120153277A1

公开(公告)日：2012-06-21

申请号：US13326859

申请日：2011-12-15

Applicant: Seiichiro Yaginuma ,  Tatsuya Iwasaki ,  Ryo Hayashi ,  Hideya Kumomi ,  Masaya Watanabe

Inventor： Seiichiro Yaginuma ,  Tatsuya Iwasaki ,  Ryo Hayashi ,  Hideya Kumomi ,  Masaya Watanabe

IPC: H01L29/786 ,  H01L21/34

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L29/78618

Abstract: A channel layer is formed on a substrate by using an oxide semiconductor and then a sacrificial layer of an oxide containing In, Zn and Ga and representing an etching rate greater than the etching rate of the oxide semiconductor is formed on the channel layer. Thereafter, a source electrode and a drain electrode are formed on the sacrificial layer and the sacrificial layer exposed between the source electrode and the drain electrode is removed by means of wet etching.

Abstract translation: 通过使用氧化物半导体在衬底上形成沟道层，然后在沟道层上形成包含In，Zn和Ga的氧化物的牺牲层，并且表现出大于氧化物半导体的蚀刻速率的蚀刻速率。 此后，在牺牲层上形成源电极和漏电极，通过湿蚀刻去除在源电极和漏电极之间露出的牺牲层。