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    METHOD FOR PACKAGING CIRCUITS
    1.
    发明申请
    METHOD FOR PACKAGING CIRCUITS 审中-公开

    公开(公告)号：US20190362988A1

    公开(公告)日：2019-11-28

    申请号：US16435200

    申请日：2019-06-07

    申请人： Micron Technology, Inc.

    发明人： Chia Y. Poo ,  Low Siu Waf ,  Boon Suan Jeung ,  Eng M. Koon ,  Chua Swee Kwang

    IPC分类号： H01L21/56 ,  H01L25/00 ,  H01L23/00 ,  H01L21/66 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31

    摘要： A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

    Method for packaging circuits
    2.
    发明授权
    Method for packaging circuits 有权

    公开(公告)号：US10453704B2

    公开(公告)日：2019-10-22

    申请号：US15339290

    申请日：2016-10-31

    申请人： Micron Technology, Inc.

    发明人： Chia Y. Poo ,  Low Siu Waf ,  Boon Suan Jeung ,  Eng M. Koon ,  Chua Swee Kwang

    IPC分类号： H05K3/30 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31

    摘要： A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

    Semiconductor dies with recesses, associated leadframes, and associated systems and methods
    4.
    发明授权
    Semiconductor dies with recesses, associated leadframes, and associated systems and methods 有权

    公开(公告)号：US10431531B2

    公开(公告)日：2019-10-01

    申请号：US16058496

    申请日：2018-08-08

    申请人： Micron Technology, Inc.

    发明人： Chua Swee Kwang ,  Yong Poo Chia

    IPC分类号： H01L23/495 ,  H01L23/047 ,  H01L21/48 ,  H01L29/06 ,  H01L23/00 ,  H01L23/31

    摘要： Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle.

    Method for packaging circuits
    6.
    发明授权
    Method for packaging circuits 有权

    公开(公告)号：US10811278B2

    公开(公告)日：2020-10-20

    申请号：US16435200

    申请日：2019-06-07

    申请人： Micron Technology, Inc.

    发明人： Chia Y. Poo ,  Low Siu Waf ,  Boon Suan Jeung ,  Eng M. Koon ,  Chua Swee Kwang

    IPC分类号： H05K3/30 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/66 ,  H01L23/31

    摘要： A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.