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1.发明申请公开(公告)号：US20190214378A1
公开(公告)日：2019-07-11
申请号：US15864545
申请日：2018-01-08
IPC分类号： H01L27/02 , H01L21/66 , H01L23/00 , H01L23/528 , H01L23/66 , H02H9/04 , G01R31/00 , G01R31/28
摘要： A circuit providing electrostatic discharge (ESD) protection and a method and an apparatus for testing ESD protection on an integrated circuit are described. The circuit includes a first ESD protection circuit and a test pad and a second ESD protection circuit and a second pad for the application, not probed during manufacturing of the integrated circuit. In some examples, the method includes providing a first, second, third, and fourth test current to the circuit providing ESD protection, measuring a first second, third, and fourth voltage drop across the circuit, and determining an operating condition for the first ESD protection circuit and the test pad and the second ESD protection circuit and the second bond pad based on expected values of the first voltage drop, the second voltage drop, the third voltage drop, and the fourth voltage drop.
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公开(公告)号：US10305600B2
公开(公告)日：2019-05-28
申请号：US15297457
申请日：2016-10-19
摘要： The invention comprises a multilevel optical signal system comprising two or more light source branches and an optical power-combiner, wherein each branch comprising a light source, an optical modulator and an electrical driver for the modulator, wherein each electrical driver is configured for being driven by electrical signals to drive the modulator to modulate the light generated by the light source into a corresponding 2-level data signal such that the respective 2-level data signals differs in power level.
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公开(公告)号：US11070214B1
公开(公告)日：2021-07-20
申请号：US17069894
申请日：2020-10-14
发明人： Thorkild Franck , Ulrik S. Wismar , Ran Sela
摘要： An Integrated Circuit (IC) includes a digital phase-locked loop (DPLL) circuit and DPLL Diagnostics circuitry (DPLL-DC). The DPLL circuit includes an oscillator, a digital phase detector and a digital feedback bus (DPLL-DFB). The oscillator is configured to generate an output signal. The digital phase detector is configured to generate a digital feedback signal indicative of a phase difference between the output signal and a reference input signal. The DPLL-DFB is configured to feed-back the digital feedback signal for controlling the oscillator. The DPLL-DC is coupled to the DPLL-DFB and is configured to monitor events depending at least on the digital feedback signal transferred on the DPLL-DFB.
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4.发明授权公开(公告)号：US10523471B2
公开(公告)日：2019-12-31
申请号：US15941831
申请日：2018-03-30
摘要： Embodiments are disclosed for equalizing a pulse amplitude modulation signal for a receiver in a communication system. An example method includes receiving an electronic signal. The electronic signal encodes a plurality of symbols in a number of amplitude levels in a plurality of pulses in the electronic signal. The example method further includes estimating multiple symbol values using all possible values of an immediately preceding symbol for each symbol in the electronic signal. Each estimated symbol value is determined using one of the possible values of the immediately preceding symbol. The example method further includes receiving an actual value of the immediately preceding symbol and selecting an actual estimated symbol value from the multiple symbol values based on the actual value of the immediately preceding symbol. The actual estimated symbol value may be used as the actual value for selecting an estimated symbol value of an immediately subsequent symbol.
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公开(公告)号：US10686528B2
公开(公告)日：2020-06-16
申请号：US16182964
申请日：2018-11-07
IPC分类号： H04B10/54 , H01S5/42 , H04B10/58 , H04B10/524
摘要： Embodiments are disclosed for generating a lookup table value for calibrating a lookup table circuit in an optical transmitter. The example method includes generating a calibration signal. The calibration signal encodes a plurality of bits in a number of amplitude levels. The example method further includes transmitting the calibration signal to a module under calibration and transmitting a symbol sequence of defined length to a reference module. The reference module compares the symbol sequence with a distorted signal received from the module under calibration to generate a set of condition count statistics. The example method further includes receiving the set of condition count statistics from the receiver in the reference module and calculating a lookup table value based on the set of condition count statistics. The example method further includes transmitting the lookup table value to a transmitter associated with the module under calibration.
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公开(公告)号：US10522529B2
公开(公告)日：2019-12-31
申请号：US15864545
申请日：2018-01-08
IPC分类号： H01L27/02 , H01L21/66 , H01L23/00 , H01L23/528 , H01L23/66 , G01R31/00 , G01R31/28 , H02H9/04
摘要： A circuit providing electrostatic discharge (ESD) protection and a method and an apparatus for testing ESD protection on an integrated circuit are described. The circuit includes a first ESD protection circuit and a test pad and a second ESD protection circuit and a second pad for the application, not probed during manufacturing of the integrated circuit. In some examples, the method includes providing a first, second, third, and fourth test current to the circuit providing ESD protection, measuring a first second, third, and fourth voltage drop across the circuit, and determining an operating condition for the first ESD protection circuit and the test pad and the second ESD protection circuit and the second bond pad based on expected values of the first voltage drop, the second voltage drop, the third voltage drop, and the fourth voltage drop.
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