公开(公告)号：US11949920B2

公开(公告)日：2024-04-02

申请号：US17871976

申请日：2022-07-24

Applicant: MEDIATEK INC.

Inventor： Ming-Hsien Lai ,  Min-Hao Chiu ,  Chia-Yun Cheng

IPC: H04N19/89 ,  H04N19/176 ,  H04N19/60 ,  H04N19/70

CPC classification number: H04N19/89 ,  H04N19/176 ,  H04N19/60 ,  H04N19/70

Abstract: A video decoding method includes: before residual decoding of a coding unit is completed, referring to available information to determine whether to decode information that an inverse transform (IT) circuit needs for applying inverse transform to transform blocks of the coding unit, and generating a determination result; and controlling coefficient transmission of the coding unit to the IT circuit according to the determination result.

公开(公告)号：US10659794B2

公开(公告)日：2020-05-19

申请号：US16293647

申请日：2019-03-06

Applicant: MEDIATEK INC.

Inventor： Chi-Min Chen ,  Min-Hao Chiu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/124 ,  H04N19/186 ,  H04N19/182 ,  H04N19/91 ,  H04N19/157 ,  H04N19/44 ,  H04N19/119

Abstract: A palette decoding apparatus includes a palette color storage device which stores palette colors, a color index storage device which stores color indices of pixels, and a palette value processing circuit which generates a palette value for each pixel by reading data from the color index storage device and the palette color storage device. A frame is divided into first coding units, and each first coding unit is sub-divided into one or more second coding units. Before a palette value of a last pixel in a first coding unit is generated by the palette value processing circuit, a palette value of a non-last pixel in the first coding unit is generated by the palette value processing circuit and used by a reconstruction circuit of the video decoder.

公开(公告)号：US10397588B2

公开(公告)日：2019-08-27

申请号：US15578184

申请日：2016-06-03

Applicant: MEDIATEK INC.

Inventor： Tzu-Der Chuang ,  Ping Chao ,  Ching-Yeh Chen ,  Yu-Chen Sun ,  Chih-Ming Wang ,  Chia-Yun Cheng ,  Han-Liang Chou ,  Yu-Wen Huang

IPC: H04N19/186 ,  H04N19/51 ,  H04N19/593 ,  H04N19/423 ,  H04N19/433 ,  H04N19/176 ,  H04N19/70

Abstract: A method and apparatus of sharing an on-chip buffer or cache memory for a video coding system using coding modes including Inter prediction mode or Intra Block Copy (IntraBC) mode are disclosed. At least partial pre-deblocking reconstructed video data of a current picture is stored in an on-chip buffer or cache memory. If the current block is coded using IntraBC mode, the pre-deblocking reconstructed video data of the current picture stored in the on-chip buffer or cache memory are used to derive IntraBC prediction for the current block. In some embodiments, if the current block is coded using Inter prediction mode, Inter reference video data from the previous picture stored in the on-chip buffer or cache memory are used to derive Inter prediction for the current block. In another embodiment, the motion compensation/motion estimation unit is shared by the two modes.

公开(公告)号：US20190123833A1

公开(公告)日：2019-04-25

申请号：US16163581

申请日：2018-10-18

Applicant: MEDIATEK INC.

Inventor： Min-Hao Chiu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04B10/69 ,  G06T9/00 ,  H04N19/70 ,  H04N19/184

Abstract: A decoding apparatus is used for decoding region of interest (ROI) regions in an image, and includes a storage device, a pre-processing circuit, a decoding circuit, and an information fetching circuit. The pre-processing circuit performs a syntax pre-parsing operation upon a bitstream to obtain necessary information of the ROI regions, and stores the necessary information into the storage device. The decoding circuit performs a decoding operation upon the bitstream to decode the ROI regions, wherein the decoding operation includes syntax parsing of the bitstream. The information fetching circuit reads and analyzes the necessary information, and delivers at least a portion of the necessary information to the decoding circuit. A processing time of obtaining necessary information of one ROI region at the pre-processing circuit overlaps a processing time of decoding another ROI region at the decoding circuit.

公开(公告)号：US10104397B2

公开(公告)日：2018-10-16

申请号：US14716904

申请日：2015-05-20

Applicant: MEDIATEK INC.

Inventor： Meng-Jye Hu ,  Yung-Chang Chang ,  Chia-Yun Cheng

IPC: H04N19/593 ,  H04N19/51 ,  H04N19/55 ,  H04N19/563 ,  H04N19/44 ,  H04N19/423

Abstract: A video processing apparatus includes a reconstruct circuit, a storage device, and an intra prediction circuit. The reconstruct circuit generates reconstructed pixels of a first block of a picture. The storage device at least stores a portion of the reconstructed pixels of the first block, wherein a capacity of the storage device is smaller than a reconstructed data size of the picture. The intra prediction circuit performs intra prediction of a second block of the picture based at least partly on pixel data obtained from the storage device.

公开(公告)号：US10075722B1

公开(公告)日：2018-09-11

申请号：US14537850

申请日：2014-11-10

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Shun-Hsiang Chuang ,  Yung-Chang Chang

IPC: H04N19/44 ,  H04N7/12 ,  H04J3/06 ,  H04N7/18 ,  H04N11/02

CPC classification number: H04N19/436 ,  H04N19/423

Abstract: A multi-core video decoder system includes a plurality of video decoder cores and a storage device. The video decoder cores are used to decode a picture, wherein each of the video decoder cores decodes a portion of the picture. The storage device has at least one shared storage space accessed by different video decoder cores of the video decoder cores. In addition, an associated video decoding method includes: performing a plurality of video decoding operations to decode a picture, wherein each of the video decoding operations decodes a portion of the picture; and controlling different video decoding operations of the video decoding operations to access at least one shared storage space.

公开(公告)号：US20180139464A1

公开(公告)日：2018-05-17

申请号：US15803388

申请日：2017-11-03

Applicant: MEDIATEK INC.

Inventor： Min-Hao CHIU ,  Ping Chao ,  Chia-Hung Kao ,  Huei-Min Lin ,  Hsiu-Yi Lin ,  Chi-Hung Chen ,  Chia-Yun Cheng ,  Chih-Ming Wang ,  Yung-Chang Chang

IPC: H04N19/44 ,  H04N19/423 ,  H04N19/172

Abstract: Aspects of the disclosure provide a video decoding system. The video decoding system can include a decoder core configured to selectively decode independently decodable tiles in a picture, each tile including largest coding units (LCUs) each associated with a pair of picture-based (X, Y) coordinates or tile-based (X, Y) coordinates, and memory management circuitry configured to translate one or two coordinates of a current LCU to generate one or two translated coordinates, and to determine a target memory space storing reference data for decoding the current LCU based on the one or two translated coordinates.

公开(公告)号：US20180020221A1

公开(公告)日：2018-01-18

申请号：US15641224

申请日：2017-07-04

Applicant: MEDIATEK INC.

Inventor： Ming-Long Wu ,  Tung-Hsing Wu ,  Li-Heng Chen ,  Ting-An Lin ,  Yi-Hsin Huang ,  Chung-Hua Tsai ,  Chia-Yun Cheng ,  Han-Liang Chou ,  Yung-Chang Chang

IPC: H04N19/13 ,  H04N21/2665 ,  H04N21/2365 ,  H04N21/2343 ,  H04N19/70 ,  H04N19/44 ,  H04N19/172 ,  H04N21/845 ,  H04N19/124

CPC classification number: H04N19/13 ,  H04N19/124 ,  H04N19/172 ,  H04N19/174 ,  H04N19/18 ,  H04N19/44 ,  H04N19/70 ,  H04N21/234363 ,  H04N21/2365 ,  H04N21/2665 ,  H04N21/8456

Abstract: A video encoder has a processing circuit and a universal binary entropy (UBE) syntax encoder. The processing circuit processes pixel data of a video frame to generate encoding-related data, wherein the encoding-related data comprise at least quantized transform coefficients. The UBE syntax encoder processes a plurality of syntax elements to generate UBE syntax data. The encoding-related data are represented by the syntax elements. The processing circuit operates according to a video coding standard. The video coding standard supports arithmetic encoding. The UBE syntax data contain no arithmetic-encoded syntax data.

公开(公告)号：US20170195693A1

公开(公告)日：2017-07-06

申请号：US15468132

申请日：2017-03-24

Applicant: MEDIATEK INC.

Inventor： Sheng-Jen Wang ,  Yung-Chang Chang ,  Chia-Yun Cheng

IPC: H04N19/91 ,  H04N19/423

CPC classification number: H04N19/91 ,  H04N19/423

Abstract: A backward adaptation apparatus includes a first storage apparatus, a count table maintenance apparatus, and a backward probability update circuit. The first storage apparatus has a first buffer and a second buffer allocated therein. The first buffer stores a first probability table involved in processing of a first frame. The second buffer stores a second probability table selectable for processing of a second frame following the first frame. The count table maintenance apparatus maintains a count table, wherein the count table maintenance apparatus has at least one count data updating circuit shared for dynamically updating the count table during the processing of the first frame. The backward probability update circuit refers to information of the count table and information of the first probability table to calculate the second probability table in the second buffer at an end of the processing of the first frame.

公开(公告)号：US20160241860A1

公开(公告)日：2016-08-18

申请号：US15139345

申请日：2016-04-27

Applicant: MEDIATEK INC.

Inventor： Min-Hao Chiu ,  Chia-Yun Cheng ,  Chun-Chia Chen

IPC: H04N19/176 ,  H04N19/122 ,  H04N19/13 ,  H04N19/124

CPC classification number: H04N19/176 ,  H04N19/12 ,  H04N19/122 ,  H04N19/124 ,  H04N19/129 ,  H04N19/13

Abstract: An exemplary video decoding apparatus includes a first decoding unit configured for decoding a first encoded block to generate first residual values, a first detecting unit configured for detecting whether all of the first residual values have a same first value, a first processing circuit configured for processing the first residual values to generate first processed residual values, and a second processing circuit configured for generating a decoded block corresponding to the first encoded block. When all of the first residual values have the same first value, the first detecting unit controls the second processing circuit to generate the decoded block without referring to the first processed residual values.