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公开(公告)号：US5445806A
公开(公告)日：1995-08-29
申请号：US845670
申请日：1992-03-04
IPC分类号： C01B13/36 , C01G23/00 , C01G25/00 , C01G30/00 , C01G30/02 , C01G33/00 , C01G49/00 , C01F5/00 , C01F11/00
CPC分类号： C01G33/00 , C01B13/363 , C01G23/003 , C01G23/006 , C01G25/006 , C01G30/00 , C01G30/026 , C01G49/009 , C01P2002/34 , C01P2002/72 , C01P2002/77 , C01P2004/03 , C01P2004/52 , C01P2004/62 , C01P2006/32 , C01P2006/80
摘要： A process for preparing a fine powder of perovskite-type compounds having an average particle size of at most 0.3 .mu.m and uniform particle sizes, which comprises subjecting to a reaction an aqueous solution of a mixture of at least one compound selected from group A element compounds comprising alkaline earth metal elements and/or bivalent metal elements with at least one compound selected from group B element compounds comprising tetravalent metal elements such as Ti, Zr, Hf and Sn and/or composite metal elements composed of a bivalent or trivalent metal element such as Zn, Ni, Co, Mg, Fe or Sb and a pentavalent metal element such as Nb or Sb in an A/B atomic ratio of more than 1, calcining the resulting powdery reaction product at a temperature which is lower than the temperature at which the growth of particles takes place and which is higher than the temperature at which the growth of particles takes place when A/B is 1, and cleaning the calcined product with an acid solution to remove the excess group A elements. The process provides fine powders of perovskite-type compounds having a good crystallinity, particularly tetragonal barium titanate, which are useful particularly as raw materials of ceramics for electronic devices.
摘要翻译： 一种平均粒径为0.3μm以上且平均粒径的钙钛矿型化合物的微细粉末的制造方法，其特征在于，将至少一种选自A族元素的化合物的混合物的水溶液 包含碱土金属元素和/或二价金属元素的化合物与至少一种选自包含四价金属元素如Ti，Zr，Hf和Sn的B族元素化合物和/或由二价或三价金属元素组成的复合金属元素 例如Zn，Ni，Co，Mg，Fe或Sb以及A / B原子比大于1的Nb或Sb的五价金属元素，在低于温度的温度下煅烧所得粉末状反应产物 当A / B为1时，发生颗粒的生长并且高于发生颗粒生长的温度，并且用酸溶液将煅烧产物清洗成r 排除多余的A组元素。 该方法提供具有良好结晶度的钙钛矿型化合物的细粉末，特别是四方晶系钛酸钡，其特别用作电子器件用陶瓷的原料。
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公开(公告)号：US06828846B2
公开(公告)日：2004-12-07
申请号：US10300807
申请日：2002-11-21
IPC分类号： H03K1762
CPC分类号： H03K17/6874 , H03K17/165 , H03K17/6872 , H03K2217/0018
摘要： An analog switch circuit includes: an analog switch composed of a first P-channel MOS transistor and a first N-channel transistor, a gate of which receives a control signal; a comparison circuit comparing potentials of a first input-output-terminal and a second input-output terminal, and conveying a higher potential to a well where the first P-channel MOS transistor is formed; a first potential conveying circuit conveying a potential of the well where the first P-channel MOS transistor is formed to a gate of the first P-channel MOS transistor when the analog switch is in the OFF state; a second potential conveying circuit operating on the basis of a control signal to convey the potential of the well where the first P-channel MOS transistor is formed to the gate of the first P-channel MOS transistor to turn off the first P-channel MOS transistor; and a third potential conveying section operating on the basis of the control signal to turn on the first P-channel MOS transistor.
摘要翻译： 模拟开关电路包括：由第一P沟道MOS晶体管和第一N沟道晶体管构成的模拟开关，其栅极接收控制信号; 比较电路，比较第一输入 - 输出端和第二输入 - 输出端的电位，并向形成第一P沟道MOS晶体管的阱传送更高的电位; 当所述模拟开关处于截止状态时，将形成所述第一P沟道MOS晶体管的阱的电势传送到所述第一P沟道MOS晶体管的栅极的第一潜在输送电路; 基于控制信号操作的第二电位传送电路，以将形成有第一P沟道MOS晶体管的阱的电位传送到第一P沟道MOS晶体管的栅极，以将第一P沟道MOS 晶体管 以及第三电位输送部，其基于所述控制信号进行工作，以导通所述第一P沟道MOS晶体管。
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公开(公告)号：US5831449A
公开(公告)日：1998-11-03
申请号：US844663
申请日：1997-04-21
IPC分类号： G06F3/00 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/094 , H03K19/0948
CPC分类号： H03K19/09429 , H03K19/00315 , H03K19/018521
摘要： An output circuit comprising an output stage and a control signal generator. The output stage is constituted by a first P-channel MOS transistor and an N-channel MOS transistor. The control signal generator generates a signal for driving the gates of the MOS transistors, it comprises a NAND gate, a NOR gate NOR1 and an inverter INV1. The first P-channel MOS transistor of the output stage has a source and a back gate which are isolated in terms of potential. A second P-channel MOS transistor is provided, whose source-drain path is connected between the back gate and gate of the first P-channel MOS transistor incorporated in the output stage.
摘要翻译： 一种输出电路，包括输出级和控制信号发生器。 输出级由第一P沟道MOS晶体管和N沟道MOS晶体管构成。 控制信号发生器产生用于驱动MOS晶体管的栅极的信号，它包括与非门，或非门NOR1和反相器INV1。 输出级的第一P沟道MOS晶体管有一个源极和一个背电极，它们是以电位方式隔离的。 提供了第二P沟道MOS晶体管，其源极 - 漏极路径连接在并入输出级的第一P沟道MOS晶体管的背栅极和栅极之间。
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公开(公告)号：US5739702A
公开(公告)日：1998-04-14
申请号：US704995
申请日：1996-08-29
IPC分类号： H03K3/356 , H03K19/0175
CPC分类号： H03K3/356104
摘要： The bus hold circuit comprises: an input stage inverter (IN1) connected between a first supply voltage (Vcc) terminal and a second supply voltage (Vss) terminal and including: a first P-channel transistor (P1); and a first N-channel transistor (N1) connected in series to the first P-channel transistor, a gate of the first P-channel transistor and a gate of the first N-channel transistor being connected in common to a bus line (INA); and an output stage inverter (IN2) also connected between the first supply voltage (Vcc) terminal and the second supply voltage (Vss) terminal and including: a second P-channel transistor (P4); a third P-channel transistor (P2) connected in series to the second P-channel transistor; and a second N-channel transistor (N2) connected in series to the third P-channel transistor, a gate of the second P-channel transistor (P4) being connected to the bus line (Lout), a gate of the third P-channel transistor (P2) and a gate of the second N-channel transistor (N2) being connected in common to a drain of the first P-channel transistor (P1) and a drain of the first N-channel transistor (N1), a drain of the third P-channel transistor (P2) and a drain of the second N-channel transistor (N2) being connected in common to the bus line (Lout). In particular, back gates (i.e., the N-type well) of the first second and third P-channel transistors (P1, P4 and P2) are all connected to a source of the P-channel transistor (P2), respectively. Therefore, it is possible to prevent unnecessary current from flowing to the supply voltage terminal of the bus hold circuit, even if an output circuit supplied with a supply voltage different from that of the bus hold circuit is connected to the bus line.
摘要翻译： 总线保持电路包括：连接在第一电源电压（Vcc）端子和第二电源电压（Vss）端子之间的输入级反相器（IN1），包括：第一P沟道晶体管（P1）; 和与第一P沟道晶体管串联连接的第一N沟道晶体管（N1），第一P沟道晶体管的栅极和第一N沟道晶体管的栅极共同连接到总线（INA ）; 以及还连接在第一电源电压（Vcc）端子和第二电源电压（Vss）端子之间的输出级反相器（IN2），包括：第二P沟道晶体管（P4）; 与第二P沟道晶体管串联连接的第三P沟道晶体管（P2）; 和与第三P沟道晶体管串联连接的第二N沟道晶体管（N2），第二P沟道晶体管（P4）的栅极连接到总线（Lout），第三P沟道晶体管的栅极 沟道晶体管（P2）和第二N沟道晶体管（N2）的栅极共同连接到第一P沟道晶体管（P1）的漏极和第一N沟道晶体管（N1）的漏极， 第三P沟道晶体管（P2）的漏极和第二N沟道晶体管（N2）的漏极共同连接到总线（Lout）。 特别地，第一第二和第三P沟道晶体管（P1，P4和P2）的背栅极（即N型阱）分别连接到P沟道晶体管（P2）的源极。 因此，即使提供了与总线保持电路不同的电源电压的输出电路连接到总线线路，也可以防止不必要的电流流向总线保持电路的电源电压端子。
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公开(公告)号：US5493233A
公开(公告)日：1996-02-20
申请号：US353397
申请日：1994-12-02
IPC分类号： H01L27/04 , H01L21/822 , H03K19/003 , H03K19/0175 , H03K17/16
CPC分类号： H03K19/00315
摘要： A transistor circuit apparatus comprises a MOS transistor to be improved, for preventing an avalanche breakdown, the MOS transistor being connected in a channel conductor path provided between one of power supply terminals and a terminal of an output, a separate circuit connected to the output terminal and driven by a voltage from a separate power supply, and a pull-down unit including a second transistor connected between one of said power supply terminals and a back gate of the MOS transistor, the second transistor being turned on with an output node of the separate circuit used as power supply when the MOS transistor remains at a ground potential level with no power supply potential supplied, thereby pulling down the potential level of a back gate node of the MOS transistor to the level of one of the power supply terminals.
摘要翻译： 一种晶体管电路装置，其特征在于，具有改善的MOS晶体管，用于防止雪崩击穿，MOS晶体管连接在设置在电源端子和输出端子之间的沟道导体路径中，与输出端子连接的分立电路 并且由来自单独的电源的电压驱动，以及下拉单元，其包括连接在所述电源端子之一和所述MOS晶体管的背栅之间的第二晶体管，所述第二晶体管由所述第二晶体管的输出节点导通， 当MOS晶体管保持在没有电源电位的接地电位电平时用作电源的单独电路，从而将MOS晶体管的背栅极节点的电位下降到电源端子之一的电平。
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公开(公告)号：US6097217A
公开(公告)日：2000-08-01
申请号：US210761
申请日：1998-12-14
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/00315
摘要： Either the power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to an output terminal while the power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to a pn-junction provided between the drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.
摘要翻译： 电源电位或接地电位通过开关施加到电源节点。 当在电源节点连接到接地电位节点的同时将高于接地电位的电位施加到输出端子时，结合在输出部分中的第一PMOS晶体管的背栅极的电位根据 由于设置在第一PMOS晶体管的漏极和背栅之间的pn结，输出端子的电位。 此时，源极 - 漏极路径连接在第一PMOS晶体管的背栅极和栅极之间的第二PMOS晶体管导通，由此第一PMOS晶体管的背栅极的电位被传送到其栅极。
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公开(公告)号：US6020778A
公开(公告)日：2000-02-01
申请号：US64814
申请日：1998-04-23
IPC分类号： H03K19/0944 , H03K17/06 , H03K17/16 , H03K17/687
CPC分类号： H03K17/162 , H03K17/063 , H03K17/6872 , H03K2217/0018
摘要： Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.
摘要翻译： 晶体管（P1，N1）中的每一个的两个端子连接在两个端子（A，B）之间。 配置晶体管（P1）的体效应补偿电路（COMP-P1）和晶体管（N1）的体效应补偿电路（COMP-N1）。 电路（COMP-P1）中的晶体管（P1P，P2P）的背栅和电路（COMP-N1）中的晶体管（P1N，P2N）共同连接到晶体管（P1）的背栅极。 电路（COMP-N1）中的晶体管（N1N，N2N）的背栅和电路（COMP-P1）中的晶体管（N1P，N2P）共同连接到晶体管（N1）的背栅极。 利用这种结构，在将信号从一个端子（A或B）传送到另一个端子（B或A）或反之后，信号电位以高速传输到晶体管（P1，N1）的背栅极 以增加信号传输速度。
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8.发明授权Protection circuit which prevents avalanche breakdown in a fet by having a floating substrate and a voltage controlled gate 失效保护电路，其通过具有浮置衬底和电压控制栅极来防止胎儿中的雪崩击穿
公开(公告)号：US5539327A
公开(公告)日：1996-07-23
申请号：US353383
申请日：1994-12-02
IPC分类号： H01L29/78 , H01L27/02 , H03K17/0812 , H03K19/003 , H02H9/04
CPC分类号： H03K19/00315 , H01L27/0251 , H03K17/08122
摘要： A transistor circuit comprises a MOS transistor with an open back gate, and control means for controlling a voltage to be applied to the control gate of the MOS transistor, whereby the control means controls the avalanche breakdown voltage of a parasitic bipolar transistor formed by the drain, back gate and source of the MOS transistor.
摘要翻译： 晶体管电路包括具有开路背栅的MOS晶体管和用于控制施加到MOS晶体管的控制栅极的电压的控制装置，由此控制装置控制由漏极形成的寄生双极晶体管的雪崩击穿电压 ，MOS晶体管的背栅极和源极。
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公开(公告)号：US5442307A
公开(公告)日：1995-08-15
申请号：US226683
申请日：1994-04-12
IPC分类号： H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018507 , H03K19/018521 , H03K2217/0018
摘要： An interface circuit includes first and second MOS transistors of depletion type, first and second switching elements, and a control circuit. The current path of the first MOS transistor is connected between an output node of a MOS circuit formed in a semiconductor substrate and an output terminal and the gate thereof is connected to a power supply. The first switching element is connected between the backgate of the first MOS transistor and a ground terminal. The second switching element and the current path of the second MOS transistor are serially connected between the backgate of the first MOS transistor and the output terminal. The gate of the second MOS transistor is connected to the power supply and the backgate thereof is connected to the backgate of the first MOS transistor. The first and second switching elements are set into complementary states according to an output of the MOS circuit in response to an output signal of the control circuit.
摘要翻译： 接口电路包括耗尽型，第一和第二开关元件的第一和第二MOS晶体管和控制电路。 第一MOS晶体管的电流路径连接在形成在半导体衬底中的MOS电路的输出节点和输出端子之间，并且其栅极连接到电源。 第一开关元件连接在第一MOS晶体管的背栅和接地端子之间。 第二开关元件和第二MOS晶体管的电流路径串联连接在第一MOS晶体管的背栅和输出端之间。 第二MOS晶体管的栅极连接到电源，并且其背栅极连接到第一MOS晶体管的背栅。 响应于控制电路的输出信号，第一和第二开关元件根据MOS电路的输出设置为互补状态。
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公开(公告)号：US5389834A
公开(公告)日：1995-02-14
申请号：US975482
申请日：1992-11-12
IPC分类号： H03K17/687 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0948
CPC分类号： H03K19/01721 , H03K19/00361
摘要： This invention discloses a signal output circuit including DC and AC buffers having output nodes commonly connected to a signal output terminal, and an AC buffer control circuit for driving the AC buffer when an output from the DC buffer is changed and for controlling an output from the AC buffer in a high-impedance state when the output from the DC buffer is stationary.
摘要翻译： 本发明公开了一种信号输出电路，包括具有共同连接到信号输出端子的输出节点的DC和AC缓冲器，以及用于在DC缓冲器的输出改变时用于驱动AC缓冲器的AC缓冲器控制电路， 交流缓冲器在高阻抗状态时，直流缓冲器的输出是静止的。
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