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公开(公告)号：US20240154712A1
公开(公告)日：2024-05-09
申请号：US18415883
申请日：2024-01-18
发明人： Bar Shapira , Ariel Almog , Dotan David Levi , Natan Manevich , Thomas Kernen , Liron Mula
IPC分类号： H04J3/06
CPC分类号： H04J3/0638
摘要： A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.
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公开(公告)号：US20240089211A1
公开(公告)日：2024-03-14
申请号：US18509810
申请日：2023-11-15
发明人： Liron Mula , Zachy Haramaty , Shachar Bar Tikva , Dekel Dadon
摘要： A relay device is provided that may identify a quantity of empty data byte locations in a data buffer of the relay device. The relay device may receive an indicator associated with transmitting data packets. The relay device may pause or enable a lossless flow of data between the relay device, a host device, and a peer device based on the quantity of empty data byte locations, the indicator, or both. The relay device may include a first data interface coupled with a peer device, a second data interface coupled with a host device, a data buffer configured to store data packets received from the host device, and a state machine that enables a lossless transmission of data between the host device and peer device. The state machine may transmit a pause frame to the host device based on a data buffer utilization reaching a data storage capacity.
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公开(公告)号：US11838209B2
公开(公告)日：2023-12-05
申请号：US17335312
申请日：2021-06-01
发明人： Matty Kadosh , Gil Levy , Yuval Shpigelman , Omer Shabtai , Yonatan Piasetzky , Liron Mula
摘要： Devices, methods, and systems are provided. In one example, a method is described to include measuring a cardinality of actual data flows at a flow-processing resource, determining that the cardinality of the actual data flows triggers a congestion control action, and, in response to determining that the cardinality of the actual data flows triggers the congestion control action, implementing the congestion control action with respect to the flow-processing resource.
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公开(公告)号：US20230185600A1
公开(公告)日：2023-06-15
申请号：US17549949
申请日：2021-12-14
发明人： Wojciech Wasko , Dotan David Levi , Liron Mula , Natan Manevich
CPC分类号： G06F9/4825 , G06F9/485 , G06F13/1689 , G06F1/08
摘要： In one embodiment, a system includes a memory, a processing device including a device processor; and a device clock, and a peripheral device including an interface to share data with the processing device, a hardware clock, and processing circuitry to write respective interrupt signaling messages to the memory responsively to respective hardware clock values of the hardware clock, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.
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公开(公告)号：US20230047454A1
公开(公告)日：2023-02-16
申请号：US17398677
申请日：2021-08-10
发明人： Liron Mula , Zachy Haramaty , Shachar Bar Tikva , Dekel Dadon
IPC分类号： H04L12/823 , H04L12/835
摘要： A relay device is provided that may identify a quantity of empty data byte locations in a data buffer of the relay device. The relay device may receive an indicator associated with transmitting data packets. The relay device may pause or enable a lossless flow of data between the relay device, a host device, and a peer device based on the quantity of empty data byte locations, the indicator, or both. The relay device may include a first data interface coupled with a peer device, a second data interface coupled with a host device, a data buffer configured to store data packets received from the host device, and a state machine that enables a lossless transmission of data between the host device and peer device. The state machine may transmit a pause frame to the host device based on a data buffer utilization reaching a data storage capacity.
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公开(公告)号：US11425230B2
公开(公告)日：2022-08-23
申请号：US17160407
申请日：2021-01-28
发明人： Liron Mula , Aviv Kfir , Amir Mizrahi , Niv Aibester
IPC分类号： H04L49/354 , H04L49/90 , H04L69/22 , H04L69/12
摘要： A parsing apparatus includes an interface, a first parser, a second parser and a controller. The interface is configured to receive packets belonging to a plurality of predefined packet types. The first parser is configured to identify any of the packet types. The second parser is configured to identify only a partial subset of the packet types. The controller is configured to receive a packet via the interface, to attempt identifying a packet type of the received packet using the second parser, and in response to detecting that identifying the packet type using the second parser fails, to revert to identify the packet type of the received packet using the first parser.
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公开(公告)号：US20140281840A1
公开(公告)日：2014-09-18
申请号：US13839193
申请日：2013-03-15
发明人： Liron Mula , Ran Ravid , Chen Gaist , Omer Sela , Oren Tzvi Sela
IPC分类号： H03M13/15
CPC分类号： H03M13/1515 , H03M13/153 , H03M13/1575 , H03M13/3715
摘要： Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS pseudo decoder is configured to correct a small number of errors in a received codeword, while the RS decoder is configured to correct errors that are recoverable by the RS code. The RS pseudo decoder runs in parallel with the RS decoder. Once the RS pseudo decoder successfully decodes the codeword, the RS decoder may stop its processing, thereby reducing the RS decoding latency.
摘要翻译： 提供了有效的里德 - 所罗门（RS）解码的方法和系统。 RS解码单元包括RS伪解码器和RS解码器。 RS伪解码器被配置为校正接收到的码字中的少量错误，而RS解码器被配置为校正可由RS码恢复的错误。 RS伪解码器与RS解码器并行运行。 一旦RS伪解码器成功解码码字，则RS解码器可能停止其处理，从而降低RS解码延迟。
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公开(公告)号：US20240152438A1
公开(公告)日：2024-05-09
申请号：US17981508
申请日：2022-11-07
发明人： Alon Singer , Ziv Battat , Liron Mula
CPC分类号： G06F11/3037 , G06F11/079 , G06F11/3075 , G06F11/3409
摘要： An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.
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9.发明公开公开(公告)号：US20230412519A1
公开(公告)日：2023-12-21
申请号：US17844362
申请日：2022-06-20
发明人： Liron Mula , Aviv Kfir , Miri Shtaif , Eran Gil Beracha
IPC分类号： H04L47/56 , H04L43/0852 , H04L47/625
CPC分类号： H04L47/56 , H04L43/0852 , H04L47/625
摘要： A device, a switch, and a method of determining latency which exceeds a threshold are described. A task is enqueued and a time is determined based on two clocks. A time the task is dequeued is determined based on the two clocks. Based on the time of enqueue and the time of dequeue according to each of the two clocks, the task is identified as meeting or violating a service level agreement.
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公开(公告)号：US20230224262A1
公开(公告)日：2023-07-13
申请号：US17648260
申请日：2022-01-18
发明人： Ioannis (Giannis) Patronas , Michael Gandelman , Liron Mula , Aviad Levy , Lion Levi , Jose Yallouz , Paraskevas Bakopoulos , Elad Mentovich
IPC分类号： H04L49/00 , H04L49/101
CPC分类号： H04L49/3027 , H04L49/101 , H04L49/3018
摘要： Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.
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