公开(公告)号：US20230215798A1

公开(公告)日：2023-07-06

申请号：US18078056

申请日：2022-12-08

Applicant: MEDIATEK INC.

Inventor： Hui-Chi Tang ,  Shao-Chun Ho ,  Hsuan-Yi Lin ,  Pu-Shan Huang

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L2224/32225 ,  H01L24/32

Abstract: A board-level pad pattern includes a corner pad unit disposed at a corner of a surface mount region for mounting a multi-row QFN package. The corner pad unit includes at least a reversed-L-shaped pad. The reversed-L-shaped pad is disposed in proximity to an apex of the corner of the surface mount region.

公开(公告)号：US20230215797A1

公开(公告)日：2023-07-06

申请号：US18076373

申请日：2022-12-06

Applicant: MEDIATEK INC.

Inventor： Hui-Chi Tang ,  Hsuan-Yi Lin ,  Shao-Chun Ho ,  Yi-Wen Chiang ,  Pu-Shan Huang

IPC: H01L23/498 ,  H05K1/11

CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H05K1/111 ,  H05K2201/094

Abstract: A board-level pad pattern includes staggered ball pads disposed within a surface mount region for mounting a multi-row QFN package. The staggered ball pads include first ball pads arranged in a first row and second ball pads arranged in a second row. The first ball pads in the first row are arranged at two different pitches, and the second ball pads in the second row are arranged at a constant pitch.

公开(公告)号：US20230217591A1

公开(公告)日：2023-07-06

申请号：US18078022

申请日：2022-12-08

Applicant: MEDIATEK INC.

Inventor： Hui-Chi Tang ,  Shao-Chun Ho ,  Hsuan-Yi Lin ,  Pu-Shan Huang

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H05K1/113 ,  H05K1/114 ,  H05K1/181

Abstract: A board-level pad pattern includes a printed circuit board (PCB) substrate; an exposed pad region disposed within a surface mount region of the base substrate; and multiple staggered ball pads disposed within the surface mount region arranged in a ring shape around the exposed pad region. The staggered ball pads includes first ball pads arranged in a first row and second ball pads arranged in a second row. The first ball pads in the first row are arranged at two different pitches, and the second ball pads in the second row are arranged at a constant pitch. Multiple square-shaped ball pads are arranged in a third row between the exposed pad region and the staggered ball pads.

公开(公告)号：US20250038126A1

公开(公告)日：2025-01-30

申请号：US18784941

申请日：2024-07-26

Applicant: MEDIATEK INC.

Inventor： De-Wei Liu ,  Pu-Shan Huang ,  Sang-Mao Chiu ,  Shih-Yi Syu

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/055 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L23/58

Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface, and a vertical sidewall extending between the top surface and the bottom surface; an integrated circuit die mounted within a device region on the top surface of the substrate; a metal interconnect structure embedded within the device region of the substrate, wherein the integrated circuit die is electrically connected to the metal interconnect structure; and a peripheral shielding ring embedded within a peripheral region of the substrate. The peripheral region surrounds the device region. A lid is mounted on the top surface of the substrate. The lid is electrically connected with the peripheral shielding ring.

公开(公告)号：US20220165694A1

公开(公告)日：2022-05-26

申请号：US17510348

申请日：2021-10-25

Applicant: MEDIATEK INC.

Inventor： Pu-Shan Huang

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/532

Abstract: A semiconductor structure includes a substrate, a passivation layer on the substrate, a post-passivation interconnect (PPI) structure on the passivation layer, and a polymer layer covering the PPI structure and the passivation layer. The PPI structure includes a step structure disposed on the passivation layer and around a lower edge of the PPI structure.