公开(公告)号：US20210141016A1

公开(公告)日：2021-05-13

申请号：US17065493

申请日：2020-10-07

Applicant: MEDIATEK INC.

Inventor： Ko-Ching Su

IPC: G01R31/3185 ,  G01R31/319

Abstract: A multi-chip system includes a plurality of chips and a monitoring and calibration system. The plurality of chips include at least a first chip and a second chip, wherein an output port of the first chip is connected to an input port of the second chip via a chip-to-chip connection, the first chip transmits an output signal to the second chip via the chip-to-chip connection, and the second chip processes an input signal that is derived from the output signal transmitted via the chip-to-chip connection. The monitoring and calibration system calibrates a chip setting of at least one of the first chip and the second chip for pulse width calibration of the input signal.

公开(公告)号：US20230386525A1

公开(公告)日：2023-11-30

申请号：US18124576

申请日：2023-03-22

Applicant: MEDIATEK INC.

Inventor： Bo-Yun Lin ,  Fan-Wei Liao ,  Tai-Ying Jiang ,  Ko-Ching Su ,  Chun-Yueh Kuo

IPC: G11C5/14 ,  G11C5/06

CPC classification number: G11C5/147 ,  G11C5/06

Abstract: A semiconductor die includes an on-die power switch and a target device. The on-die power switch includes a plurality of power input nodes, a power output node, and a switch circuit. The power input nodes receive a plurality of operation voltages from a plurality of different power sources, respectively. The power output node outputs a target operation voltage selected from the operation voltages. The switch circuit selectively couples one of the power input nodes to the power output node. The target device operates according to the target operation voltage supplied from the on-die power switch. The on-die power switch and the target device are separate circuit blocks of the semiconductor die.

公开(公告)号：US11789076B2

公开(公告)日：2023-10-17

申请号：US17065493

申请日：2020-10-07

Applicant: MEDIATEK INC.

Inventor： Ko-Ching Su

IPC: G01R31/3185 ,  G01R31/319

CPC classification number: G01R31/318513 ,  G01R31/3191

Abstract: A multi-chip system includes a plurality of chips and a monitoring and calibration system. The plurality of chips include at least a first chip and a second chip, wherein an output port of the first chip is connected to an input port of the second chip via a chip-to-chip connection, the first chip transmits an output signal to the second chip via the chip-to-chip connection, and the second chip processes an input signal that is derived from the output signal transmitted via the chip-to-chip connection. The monitoring and calibration system calibrates a chip setting of at least one of the first chip and the second chip for pulse width calibration of the input signal.