-
公开(公告)号：US11451200B2
公开(公告)日：2022-09-20
申请号：US17132166
申请日：2020-12-23
Applicant: MEDIATEK INC.
Inventor： Fong-Wen Lee , Kuan-Ta Chen
Abstract: A class-D amplifier with low pop-click noise is shown. A loop filter, a control signal generator, a first power driver, and a first feedback circuit are provided within the class-D amplifier to establish a first loop for signal amplification. The class-D amplifier further has a settling circuit and a pre-charging circuit. The settling circuit is configured to be combined with the loop filer and the control signal generator to establish a second loop to settle the loop filter and the control signal generator before the first loop is enabled. The pre-charging circuit is configured to pre-charge a positive output terminal and a negative output terminal of the first power driver.
-
公开(公告)号：US11811413B2
公开(公告)日：2023-11-07
申请号：US17864416
申请日：2022-07-14
Applicant: MEDIATEK INC.
Inventor： Fong-Wen Lee , Wen-Chieh Wang , Yu-Hsin Lin
Abstract: The present invention provides a filtering circuit comprising a poly phase filter and a quadrature phase detector. The poly phase filter comprises a first path, a second path, a third path and a fourth path. The first path is configured to receive a first input signal to generate a first clock signal. The second path comprising a first adjustable delay circuit is configured to receive the first input signal to generate a second clock signal. The third path comprising a second adjustable delay circuit is configured to receive a second input signal to generate a third clock signal. The fourth path is configured to receive the second input signal to generate a fourth clock signal. The quadrature phase detector is configured to detect phases of these clock signals to generate control signals to control the first adjustable delay circuit and the second adjustable delay circuit.
-
公开(公告)号：US20230114343A1
公开(公告)日：2023-04-13
申请号：US17864416
申请日：2022-07-14
Applicant: MEDIATEK INC.
Inventor： Fong-Wen Lee , Wen-Chieh Wang , Yu-Hsin Lin
Abstract: The present invention provides a filtering circuit comprising a poly phase filter and a quadrature phase detector. The poly phase filter comprises a first path, a second path, a third path and a fourth path. The first path is configured to receive a first input signal to generate a first clock signal. The second path comprising a first adjustable delay circuit is configured to receive the first input signal to generate a second clock signal. The third path comprising a second adjustable delay circuit is configured to receive a second input signal to generate a third clock signal. The fourth path is configured to receive the second input signal to generate a fourth clock signal. The quadrature phase detector is configured to detect phases of these clock signals to generate control signals to control the first adjustable delay circuit and the second adjustable delay circuit.
-
公开(公告)号：US11349442B2
公开(公告)日：2022-05-31
申请号：US16813630
申请日：2020-03-09
Applicant: MEDIATEK INC.
Inventor： Fong-Wen Lee , Yu-Hsin Lin
IPC: H03F3/45
Abstract: The present invention provides a differential to single-ended converter including a first input node, a second input node, an operational amplifier and a feedback circuit. The operational amplifier has a first terminal and a second terminal, wherein the first terminal of the operational amplifier receives a first signal from the first input terminal, and the second terminal of the operational amplifier receives a second signal from the second input terminal. The feedback circuit is configured to receive an output signal of the operational amplifier and generate a first feedback signal to the first terminal of the operational amplifier to reduce a swing of the first signal, and generate a second feedback signal to the second terminal of the operational amplifier to balance noises induced by the feedback circuit and inputted to the first terminal and the second terminal.
-
公开(公告)号：US20230113143A1
公开(公告)日：2023-04-13
申请号：US17857161
申请日：2022-07-04
Applicant: MEDIATEK INC.
Inventor： Fong-Wen Lee , Wen-Chieh Wang , Yu-Hsin Lin
IPC: H03L7/087 , H03L7/107 , H03L7/07 , H03K17/687
Abstract: The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.
-
Patent Agency Ranking
公开(公告)号：US20220182040A1
公开(公告)日：2022-06-09
申请号：US17503385
申请日：2021-10-18
Applicant: MEDIATEK INC.
Inventor： Fong-Wen Lee , Wen-Chieh Wang , Yu-Hsin Lin
IPC: H03H11/04
Abstract: A filter circuit includes a polyphase filter used to generate a plurality of output signals with different phases according to a plurality of input signals. The polyphase filter includes a switch circuit and a feed-forward capacitor. The switch circuit has a control terminal used to receive a control voltage, a first connection terminal used to output one of the output signals, and a second connection terminal used to receive one of the input signals. The feed-forward capacitor has a first plate coupled to the second connection terminal of the switch circuit and a second plate coupled to the control terminal of the switch circuit.
-
公开(公告)号：US20200304083A1
公开(公告)日：2020-09-24
申请号：US16813630
申请日：2020-03-09
Applicant: MEDIATEK INC.
Inventor： Fong-Wen Lee , Yu-Hsin Lin
IPC: H03F3/45
Abstract: The present invention provides a differential to single-ended converter including a first input node, a second input node, an operational amplifier and a feedback circuit. The operational amplifier has a first terminal and a second terminal, wherein the first terminal of the operational amplifier receives a first signal from the first input terminal, and the second terminal of the operational amplifier receives a second signal from the second input terminal. The feedback circuit is configured to receive an output signal of the operational amplifier and generate a first feedback signal to the first terminal of the operational amplifier to reduce a swing of the first signal, and generate a second feedback signal to the second terminal of the operational amplifier to balance noises induced by the feedback circuit and inputted to the first terminal and the second terminal.
-
公开(公告)号：US12212325B2
公开(公告)日：2025-01-28
申请号：US17857161
申请日：2022-07-04
Applicant: MEDIATEK INC.
Inventor： Fong-Wen Lee , Wen-Chieh Wang , Yu-Hsin Lin
IPC: H03L7/087 , H03K17/687 , H03L7/07 , H03L7/107
Abstract: The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.
-
公开(公告)号：US20230231551A1
公开(公告)日：2023-07-20
申请号：US17987875
申请日：2022-11-16
Applicant: MEDIATEK INC.
Inventor： Fong-Wen Lee , Wen-Chieh Wang , Yu-Hsin Lin
CPC classification number: H03K17/161 , H03H11/28
Abstract: The present invention provides a transmitter including a first variable resistor, a first transistor, a second transistor, a third transistor and a fourth transistor is disclosed. The first variable resistor is coupled between a supply voltage and a first node. A first electrode of the first transistor is coupled to the first node, and a second electrode of the first transistor is coupled to a first output terminal of the transmitter. A first electrode of the second transistor is coupled to the first output terminal of the transmitter, and a second electrode of the second transistor is coupled to a second node. A first electrode of the third/fourth transistor is coupled to the first node, and a second electrode of the third/fourth transistor is coupled to a second output terminal of the transmitter.
-
公开(公告)号：US11552602B2
公开(公告)日：2023-01-10
申请号：US17227583
申请日：2021-04-12
Applicant: MEDIATEK INC.
Inventor： Fong-Wen Lee , Wen-Chieh Wang , Yu-Hsin Lin
Abstract: A class-D amplifier with good signal-to-noise ratio (SNR) performance is shown. The class-D amplifier includes a loop filter, a pulse-width modulation signal generator, a gate driver, a power driver, and a feedback circuit, which are configured to establish a closed amplification loop. The feedback circuit is configured to establish a feedback path. The class-D amplifier further includes a feedback breaker. The feedback breaker breaks the feedback path in response to conditions in which there no-signal information in the class-D amplifier.
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.019 seconds)
