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公开(公告)号：US20220239533A1
公开(公告)日：2022-07-28
申请号：US17156437
申请日：2021-01-22
发明人： Dianyong Chen , Rajiv Shukla , Bengt Littmann
IPC分类号： H04L25/03 , H04L12/939 , H04L7/04 , G06F1/10
摘要： A combined error checker and sequence generator which shares a LFSR is disclosed which reduces complexity, cost, and area required for implementation while also improving timing margin. A clock and data recovery system recovers a data signal received over a channel from a remote transceiver. Control logic selects different modes of operation of the system. An error detector compares the two sequence signals and records errors in response to differences between the two sequence signals. A sequence generator generates a sequence signal for use by the error detector as a reference sequence signal or for transmission to a remote transceiver. The system includes one or more switching elements configured to selectively route the generated sequence as feedback into the sequence generator or the received sequence signal into the sequence generator subject to whether the combined error checker and sequence generator is in error checker mode or sequence generator mode.
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公开(公告)号：US11784856B2
公开(公告)日：2023-10-10
申请号：US17156437
申请日：2021-01-22
发明人： Dianyong Chen , Rajiv Shukla , Bengt Littmann
IPC分类号： H04L1/00 , H04L25/03 , G06F1/10 , H04L7/04 , H04L49/552
CPC分类号： H04L25/03286 , G06F1/10 , H04L7/048 , H04L49/552
摘要： A combined error checker and sequence generator which shares a LFSR is disclosed which reduces complexity, cost, and area required for implementation while also improving timing margin. A clock and data recovery system recovers a data signal received over a channel from a remote transceiver. Control logic selects different modes of operation of the system. An error detector compares the two sequence signals and records errors in response to differences between the two sequence signals. A sequence generator generates a sequence signal for use by the error detector as a reference sequence signal or for transmission to a remote transceiver. The system includes one or more switching elements configured to selectively route the generated sequence as feedback into the sequence generator or the received sequence signal into the sequence generator subject to whether the combined error checker and sequence generator is in error checker mode or sequence generator mode.
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公开(公告)号：US11409691B2
公开(公告)日：2022-08-09
申请号：US17128087
申请日：2020-12-19
发明人： Bengt Littmann
摘要： A shared bus for inter-channel communication comprising two or more channels having signal processing elements such that each channel is configured to receive and process an incoming channel specific signal. A sequence generator is configured to generate a test sequence suitable for testing the signal processing elements of a channel. An error checker is configured to error check incoming channel specific signals. A shared bus connects to the two or more channels to communicate an incoming channel specific signal to the error checker and communicate the test sequence to the signal processing elements of a channel. One or more pull up resistors and/or termination resistors connect to the shared bus. The bus may comprise a clock signal path and a data signal path. The test sequence may be a pseudo-random bit sequence. The bus interface comprises an open collector current mode logic driver in cascode arrangement.
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公开(公告)号：US20220197849A1
公开(公告)日：2022-06-23
申请号：US17128087
申请日：2020-12-19
发明人： Bengt Littmann
IPC分类号： G06F13/42 , G06F13/364 , G06F7/58
摘要： A shared bus for inter-channel communication comprising two or more channels having signal processing elements such that each channel is configured to receive and process an incoming channel specific signal. A sequence generator is configured to generate a test sequence suitable for testing the signal processing elements of a channel. An error checker is configured to error check incoming channel specific signals. A shared bus connects to the two or more channels to communicate an incoming channel specific signal to the error checker and communicate the test sequence to the signal processing elements of a channel. One or more pull up resistors and/or termination resistors connect to the shared bus. The bus may comprise a clock signal path and a data signal path. The test sequence may be a pseudo-random bit sequence. The bus interface comprises an open collector current mode logic driver in cascode arrangement.
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公开(公告)号：US10911052B2
公开(公告)日：2021-02-02
申请号：US16421376
申请日：2019-05-23
IPC分类号： H03L7/081 , H04L27/227 , G04F10/00 , G06F1/06 , G06F1/12 , G06F1/10 , H04L25/49 , H04L7/033 , H04L27/38 , H04L7/00
摘要： A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.
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公开(公告)号：US20200007133A1
公开(公告)日：2020-01-02
申请号：US16421376
申请日：2019-05-23
摘要： A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.
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