公开(公告)号：US06696856B1

公开(公告)日：2004-02-24

申请号：US10020469

申请日：2001-10-30

Applicant: Lyle Smith ,  Eric Dellinger ,  Eric West ,  Shridhar Mukund

Inventor： Lyle Smith ,  Eric Dellinger ,  Eric West ,  Shridhar Mukund

IPC: G06F738

CPC classification number: H03K19/1736

Abstract: Described herein is an ASIC having an array of predesigned function blocks. The function blocks can be used to implement combinational logic, sequential logic, or a combination of both. The function blocks also have a selectable output drive strength. The output drive strength can be selected, in some embodiments, using mask programming.

Abstract translation: 这里描述的是具有预先设计的功能块阵列的ASIC。 功能块可用于实现组合逻辑，顺序逻辑或两者的组合。 功能块也具有可选的输出驱动强度。 在一些实施例中，可以使用掩模编程来选择输出驱动强度。

公开(公告)号：US06885043B2

公开(公告)日：2005-04-26

申请号：US10051237

申请日：2002-01-18

Applicant: Lyle Smith ,  Eric Dellinger ,  Eric West ,  Shridhar Mukund

Inventor： Lyle Smith ,  Eric Dellinger ,  Eric West ,  Shridhar Mukund

IPC: H01L27/118 ,  H01I29/739

CPC classification number: H01L27/118

Abstract: An embodiment of the invention includes a routing architecture with a plurality of predesigned layers and a custom layer. The structure includes a plurality of parallel vertical tracks. In one layer, the tracks include a pin coupled to an input/output of an underlying function block and the track also includes a first portion of an unbroken conductive path. A second portion of the unbroken conductive path is formed under the pin in at least a second predesigned layer. In some embodiments, the second portion of the unbroken conductive path is formed in the second predesigned layer for some tracks and a third predesigned layer for other tracks. Hence, pins and unbroken conductive paths are multiplexed in a single track. In addition, the second predesigned layer further includes long horizontal conductors. When using the predesigned layers, the custom layer can be structured to provide free global routing with distinct local routing, all while using an array structure independent of routing channels and without rendering any function blocks unusable. Moreover, a structure in accordance with the invention includes conductors for clock distribution which can be used to form multiple independent clock domains. The structure is compact, yet flexible and can be customized in some embodiments with 1-2 masks.

Abstract translation: 本发明的实施例包括具有多个预先设计的层和定制层的路由架构。 该结构包括多个平行的垂直轨道。 在一个层中，轨迹包括一个与底层功能块的输入/输出相连的引脚，并且轨道还包括不间断导电路径的第一部分。 不间断导电路径的第二部分在至少第二预设计层中形成在引脚下方。 在一些实施例中，不间断导电路径的第二部分形成在用于一些轨道的第二预设计层中，以及用于其它轨道的第三预设计层。 因此，引脚和不间断的导电路径被复用在单个轨道中。 此外，第二预先设计的层还包括长的水平导体。 当使用预先设计的图层时，自定义图层可以被构造为提供具有不同本地路由的免费全局路由，同时使用独立于路由通道的阵列结构，并且不会使任何功能块不可用。 此外，根据本发明的结构包括可用于形成多个独立时钟域的用于时钟分配的导体。 该结构紧凑而又灵活，并且可以在具有1-2个掩模的一些实施例中进行定制。

公开(公告)号：US06861867B2

公开(公告)日：2005-03-01

申请号：US10093767

申请日：2002-03-07

Applicant: Eric West ,  Shridhar Mukund

Inventor： Eric West ,  Shridhar Mukund

IPC: G01R31/3185 ,  G06F7/38 ,  G01R31/28

CPC classification number: G01R31/318516 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/318594

Abstract: A system for remotely/automatedly testing an ASIC and particularly to testing a user-designed circuit is disclosed. In general, a system in accordance with the invention includes a plurality of cells, where the cells are couplable to form a user-designed circuit, e.g., by customizing routing. Within the ASIC and prior to any knowledge of the user-designed circuit, the ASIC includes circuitry to enable internal remote/automated testing of the user-designed circuit to be later formed. The circuitry controls the input and mode of operation of the cells and the sequencing of multiple synchronous or asynchronous clock domain inputs thereby providing testing of the user-designed circuit at speed for stuck-at-faults and delay faults.

Abstract translation: 公开了用于远程/自动测试ASIC的系统，特别是用于测试用户设计的电路的系统。 通常，根据本发明的系统包括多个单元，其中单元可耦合以形成用户设计的电路，例如通过定制路由。 在ASIC内，并且在用户设计的电路的任何知识之前，ASIC包括用于使用户稍后形成的用户设计电路的内部远程/自动测试的电路。 电路控制单元的输入和操作模式以及多个同步或异步时钟域输入的排序，从而以卡通故障和延迟故障的速度提供用户设计电路的测试。

公开(公告)号：US08122413B2

公开(公告)日：2012-02-21

申请号：US12303938

申请日：2007-06-09

Applicant: Pat Hom ,  Steven Eplett ,  Rabi Sengupta ,  Eric West ,  Lyle Smith

Inventor： Pat Hom ,  Steven Eplett ,  Rabi Sengupta ,  Eric West ,  Lyle Smith

IPC: G06F17/50

CPC classification number: G11C29/32 ,  G01R31/318541 ,  G01R31/318583 ,  G11C2029/3202

Abstract: Logic blocks for IC designs (including gate-array, standard cell, or logic array designs) provide Design-for-Test-enabled flip-flops (DFT-enabled FFs) that inherently insure compliance with DFT rules associated with scan shifting. Test scan-chains are configured by daisy-chaining instances of the logic block in a transparent (invisible) manner to user-designed application circuits, which can be designed without any user-inserted test structures or other regard for DFT considerations. User asynchronous set and reset inputs and all Stuck-At faults on all user pins on these DFT-enabled FFs are observable via capture and scan-out. A first type of these DFT-enabled FFs features addressable control to partition test the application circuit. A second type of these DFT-enabled FFs features integral capture buffering that eliminates the need for partition test, simplifying control logic and reducing the number of test vectors needed.

Abstract translation: IC设计的逻辑块（包括门阵列，标准单元或逻辑阵列设计）提供了基于设计的测试启用触发器（DFT启用FF），其固有地确保符合与扫描移位相关的DFT规则。 测试扫描链通过以透明（不可见）方式将逻辑块的菊花链实例配置为用户设计的应用电路，可以在没有任何用户插入的测试结构或其他DFT考虑因素的情况下进行设计。 用户异步设置和复位输入以及这些DFT使能的FF上所有用户引脚上的所有Stuck-At故障都可以通过捕捉和扫描显示。 这些具有DFT功能的FF的第一种功能具有可寻址的控制功能，可以对应用电路进行分区测试。 这些DFT启用的FF的第二种类型具有集成捕获缓冲功能，无需进行分区测试，简化了控制逻辑，并减少了所需的测试向量数量。

公开(公告)号：US20100169856A1

公开(公告)日：2010-07-01

申请号：US12303938

申请日：2007-06-09

Applicant: Pat Hom ,  Steven Eplett ,  Rabi Sengupta ,  Eric West ,  Lyle Smith

Inventor： Pat Hom ,  Steven Eplett ,  Rabi Sengupta ,  Eric West ,  Lyle Smith

IPC: G06F17/50 ,  G01R31/3177 ,  G06F11/25

CPC classification number: G11C29/32 ,  G01R31/318541 ,  G01R31/318583 ,  G11C2029/3202

Abstract: Logic blocks for IC designs (including gate-array, standard cell, or logic array designs) provide Design-for-Test-enabled flip-flops (DFT-enabled FFs) that inherently insure compliance with DFT rules associated with scan shifting. Test scan-chains are configured by daisy-chaining instances of the logic block in a transparent (invisible) manner to user-designed application circuits, which can be designed without any user-inserted test structures or other regard for DFT considerations. User asynchronous set and reset inputs and all Stuck-At faults on all user pins on these DFT-enabled FFs are observable via capture and scan-out. A first type of these DFT-enabled FFs features addressable control to partition test the application circuit. A second type of these DFT-enabled FFs features integral capture buffering that eliminates the need for partition test, simplifying control logic and reducing the number of test vectors needed.

Abstract translation: IC设计的逻辑块（包括门阵列，标准单元或逻辑阵列设计）提供了基于设计的测试启用触发器（DFT启用FF），其固有地确保符合与扫描移位相关的DFT规则。 测试扫描链通过以透明（不可见）方式将逻辑块的菊花链实例配置为用户设计的应用电路，可以在没有任何用户插入的测试结构或其他DFT考虑因素的情况下进行设计。 用户异步设置和复位输入以及这些DFT使能的FF上所有用户引脚上的所有Stuck-At故障都可以通过捕捉和扫描显示。 这些具有DFT功能的FF的第一种功能具有可寻址的控制功能，可以对应用电路进行分区测试。 这些DFT启用的FF的第二种类型具有集成捕获缓冲功能，无需进行分区测试，简化了控制逻辑，并减少了所需的测试向量数量。

公开(公告)号：US06680626B2

公开(公告)日：2004-01-20

申请号：US10161931

申请日：2002-06-05

Applicant: Chit-Ah Mak ,  Bingda B. Wang ,  Eric West ,  Robert A. Olah

Inventor： Chit-Ah Mak ,  Bingda B. Wang ,  Eric West ,  Robert A. Olah

IPC: H03K522

CPC classification number: H03K5/2481

Abstract: A differential receiver having a pair of cross-coupled signal conditioning devices improves transition time and data signal integrity. In an embodiment, the differential receiver includes two signal input nodes and a plurality of transistors, and two signal output nodes. The pair of cross-coupled signal conditioning devices are coupled to the transistors and function to reduce voltage swing between the two output nodes, thereby keeping the transistors in a saturation region.

Abstract translation: 具有一对交叉耦合信号调理装置的差分接收器改善了转换时间和数据信号完整性。 在一个实施例中，差分接收器包括两个信号输入节点和多个晶体管以及两个信号输出节点。 一对交叉耦合的信号调节装置耦合到晶体管并且用于减小两个输出节点之间的电压摆幅，从而将晶体管保持在饱和区域。