公开(公告)号：US06885043B2

公开(公告)日：2005-04-26

申请号：US10051237

申请日：2002-01-18

Applicant: Lyle Smith ,  Eric Dellinger ,  Eric West ,  Shridhar Mukund

Inventor： Lyle Smith ,  Eric Dellinger ,  Eric West ,  Shridhar Mukund

IPC: H01L27/118 ,  H01I29/739

CPC classification number: H01L27/118

Abstract: An embodiment of the invention includes a routing architecture with a plurality of predesigned layers and a custom layer. The structure includes a plurality of parallel vertical tracks. In one layer, the tracks include a pin coupled to an input/output of an underlying function block and the track also includes a first portion of an unbroken conductive path. A second portion of the unbroken conductive path is formed under the pin in at least a second predesigned layer. In some embodiments, the second portion of the unbroken conductive path is formed in the second predesigned layer for some tracks and a third predesigned layer for other tracks. Hence, pins and unbroken conductive paths are multiplexed in a single track. In addition, the second predesigned layer further includes long horizontal conductors. When using the predesigned layers, the custom layer can be structured to provide free global routing with distinct local routing, all while using an array structure independent of routing channels and without rendering any function blocks unusable. Moreover, a structure in accordance with the invention includes conductors for clock distribution which can be used to form multiple independent clock domains. The structure is compact, yet flexible and can be customized in some embodiments with 1-2 masks.

Abstract translation: 本发明的实施例包括具有多个预先设计的层和定制层的路由架构。 该结构包括多个平行的垂直轨道。 在一个层中，轨迹包括一个与底层功能块的输入/输出相连的引脚，并且轨道还包括不间断导电路径的第一部分。 不间断导电路径的第二部分在至少第二预设计层中形成在引脚下方。 在一些实施例中，不间断导电路径的第二部分形成在用于一些轨道的第二预设计层中，以及用于其它轨道的第三预设计层。 因此，引脚和不间断的导电路径被复用在单个轨道中。 此外，第二预先设计的层还包括长的水平导体。 当使用预先设计的图层时，自定义图层可以被构造为提供具有不同本地路由的免费全局路由，同时使用独立于路由通道的阵列结构，并且不会使任何功能块不可用。 此外，根据本发明的结构包括可用于形成多个独立时钟域的用于时钟分配的导体。 该结构紧凑而又灵活，并且可以在具有1-2个掩模的一些实施例中进行定制。

公开(公告)号：US06696856B1

公开(公告)日：2004-02-24

申请号：US10020469

申请日：2001-10-30

Applicant: Lyle Smith ,  Eric Dellinger ,  Eric West ,  Shridhar Mukund

Inventor： Lyle Smith ,  Eric Dellinger ,  Eric West ,  Shridhar Mukund

IPC: G06F738

CPC classification number: H03K19/1736

Abstract: Described herein is an ASIC having an array of predesigned function blocks. The function blocks can be used to implement combinational logic, sequential logic, or a combination of both. The function blocks also have a selectable output drive strength. The output drive strength can be selected, in some embodiments, using mask programming.

Abstract translation: 这里描述的是具有预先设计的功能块阵列的ASIC。 功能块可用于实现组合逻辑，顺序逻辑或两者的组合。 功能块也具有可选的输出驱动强度。 在一些实施例中，可以使用掩模编程来选择输出驱动强度。

公开(公告)号：US07648912B1

公开(公告)日：2010-01-19

申请号：US11277253

申请日：2006-03-23

Applicant: Eric Dellinger

Inventor： Eric Dellinger

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: H01L27/0207 ,  H01L27/11807

Abstract: Disclosed herein is an integrated circuit customized by mask programming using custom conducting layers and via layers interspersed with the custom conducting layers, where the via layers are defined by masks designed prior to receiving a custom circuit design.

Abstract translation: 本文公开了一种通过掩模编程定制的集成电路，其使用定制的导电层和散布有定制导电层的通孔层，其中通孔层由在接收定制电路设计之前设计的掩模限定。

公开(公告)号：US06613611B1

公开(公告)日：2003-09-02

申请号：US09747129

申请日：2000-12-22

Applicant: Dana How ,  Robert Osann, Jr. ,  Eric Dellinger

Inventor： Dana How ,  Robert Osann, Jr. ,  Eric Dellinger

IPC: H01L2182

CPC classification number: H01L27/118

Abstract: A customizable ASIC routing architecture is provided. The architecture utilizes the uppermost metal layers of an ASIC composed of an array of function blocks for routing among function blocks while lower layers are used for local interconnections within the function blocks. The second-to-uppermost metal layer is fixed and generally includes a plurality of parallel segmented conductors extending in a first direction. The uppermost metal layer is customizable in a predesignated manner. Metal in the uppermost metal layer is selectively placed in tracks, which are substantially perpendicular to the segmented conductors in the layer below. Vias are provided between the two uppermost layers. One embodiment of the invention permits one-mask customization of an ASIC. Other embodiments allow a determination to be made of the ideal number of custom mask steps, taking into consideration performance, cost, time, and routability.

Abstract translation: 提供可定制的ASIC路由架构。 该架构使用由功能块阵列组成的ASIC的最上层金属层，用于在功能块之间路由，而较低层用于功能块内的本地互连。 第二至第三金属层是固定的，并且通常包括沿第一方向延伸的多个平行的分段导体。 最上层的金属层可以预先指定的方式定制。 最上层金属层中的金属被选择性地放置在跟下面的层中基本上垂直于分段导体的轨道中。 在两个最上层之间提供通孔。 本发明的一个实施例允许ASIC的单掩模定制。 考虑到性能，成本，时间和可路由性，其他实施例允许确定理想数量的定制掩模步骤。

公开(公告)号：US07770144B2

公开(公告)日：2010-08-03

申请号：US10447465

申请日：2003-05-28

Applicant: Eric Dellinger

Inventor： Eric Dellinger

IPC: H03K19/00 ,  G06F17/50 ,  H01L27/10

CPC classification number: G06F17/5068 ,  H01L27/0203 ,  H01L27/118

Abstract: Disclosed herein is an ASIC having a base array of function blocks. Each function block includes a plurality of primitive cells. Each primitive cell is defined by a component from a standard cell library. The base array is prefabricated for use later with a custom circuit design.

Abstract translation: 这里公开了具有功能块的基本阵列的ASIC。 每个功能块包括多个原始单元。 每个原始单元由来自标准单元库的组件定义。 基础阵列预制用于以后使用定制电路设计。

公开(公告)号：US08504950B2

公开(公告)日：2013-08-06

申请号：US12842670

申请日：2010-07-23

Applicant: Eric Dellinger

Inventor： Eric Dellinger

IPC: G06F17/50 ,  G06F7/38 ,  H01L25/00

CPC classification number: G06F17/5068 ,  H01L27/0203 ,  H01L27/118

Abstract: Disclosed herein is an ASIC having a base array of function blocks. Each function block includes a plurality of primitive cells. Each primitive cell is defined by a component from a standard cell library. The base array is prefabricated for use later with a custom circuit design.

Abstract translation: 这里公开了具有功能块的基本阵列的ASIC。 每个功能块包括多个原始单元。 每个原始单元由来自标准单元库的组件定义。 基础阵列预制用于以后使用定制电路设计。

公开(公告)号：US20100299648A1

公开(公告)日：2010-11-25

申请号：US12842670

申请日：2010-07-23

Applicant: Eric Dellinger

Inventor： Eric Dellinger

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H01L27/0203 ,  H01L27/118

Abstract: Disclosed herein is an ASIC having a base array of function blocks. Each function block includes a plurality of primitive cells. Each primitive cell is defined by a component from a standard cell library. The base array is prefabricated for use later with a custom circuit design.

Abstract translation: 这里公开了具有功能块的基本阵列的ASIC。 每个功能块包括多个原始单元。 每个原始单元由来自标准单元库的组件定义。 基础阵列预制用于以后使用定制电路设计。

公开(公告)号：US07102237B1

公开(公告)日：2006-09-05

申请号：US10447466

申请日：2003-05-28

Applicant: Eric Dellinger

Inventor： Eric Dellinger

IPC: H01L23/48 ,  H01L27/10

CPC classification number: H01L27/0207 ,  H01L27/11807

Abstract: Disclosed herein is an integrated circuit customized by mask programming using custom conducting layers and via layers interspersed with the custom conducting layers, where the via layers are defined by masks designed prior to receiving a custom circuit design.

Abstract translation: 本文公开了一种通过掩模编程定制的集成电路，其使用定制的导电层和散布有定制导电层的通孔层，其中通孔层由在接收定制电路设计之前设计的掩模限定。