公开(公告)号：US5309561A

公开(公告)日：1994-05-03

申请号：US589847

申请日：1990-09-28

申请人： Leonard E. Overhouse ,  Daniel E. Lenoski

发明人： Leonard E. Overhouse ,  Daniel E. Lenoski

IPC分类号： G06F1/06 ,  G06F1/12 ,  G06F13/36 ,  G06F13/42 ,  G06F15/78

CPC分类号： G06F1/06 ,  G06F1/12 ,  G06F13/423

摘要： A synchronous processor unit is divided into two sections, and each separately clocked by different clock signals. One section, containing an instruction execution unit and memory for storage of instructions and data, is clocked at a higher frequency, while the other section, containing those elements of a processor unit less frequently used, are clocked with a slower-frequencied clock. The elements of each section are intercoupled by separate and independent data buses, and selectively to one another by a buffer unit. The clock signals used by both sections are produced by a clock-generating unit which also monitors the instructions being executed by the instruction execution unit. When an instruction requiring communication between the two sections is detected, at least one predetermined transition of each of the fast and slow clocks are synchronized, and during this synchronization the separate buses of each section are coupled to one another by the buffer unit for information exchanges therebetween.

摘要翻译： 同步处理器单元分为两个部分，每个部分分别由不同的时钟信号计时。 包含用于存储指令和数据的指令执行单元和存储器的一个部分以更高的频率被计时，而包含较不频繁使用的处理器单元的那些元件的另一部分被较慢频率的时钟计时。 每个部分的元件通过单独和独立的数据总线相互耦合，并且通过缓冲单元彼此选择性地相互配合。 由两部分使用的时钟信号由时钟发生单元产生，时钟发生单元还监视由指令执行单元执行的指令。 当检测到需要两部分之间的通信的指令时，快速和慢速时钟中的每一个的至少一个预定转换被同步，并且在该同步期间，每个部分的分开的总线通过用于信息交换的缓冲器单元彼此耦合 之间。

公开(公告)号：US4718065A

公开(公告)日：1988-01-05

申请号：US845918

申请日：1986-03-31

申请人： Richard F. Boyle ,  Leonard E. Overhouse

发明人： Richard F. Boyle ,  Leonard E. Overhouse

IPC分类号： G06F11/22 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/27 ,  G06F11/273 ,  G01R31/28

CPC分类号： G01R31/318335 ,  G01R31/318385 ,  G01R31/318547 ,  G06F11/27 ,  G06F11/2733

摘要： Apparatus is disclosed for generating pseudo-random bit patterns that are applied to a data processor, or other digital logic unit, for test purposes. In accordance with the invention, certain of the elemental storage units (e.g., flipflops) of the data processor are designed for two-mode operation: A normal mode of operation during which they operate as a part of the data processor in normal fashion, and a scan mode operation during which the elemental storage units respond to scan control signals to form a number of shift register or scan line configurations for receiving the pseudo-random sequenced or non-random sequenced test patterns generated by the apparatus. During testing, the bit patterns are passed through the scan line configurations and applied to compression circuits where, using cyclic redundancy checking (CRC), compression bit patterns received from the scan lines are achieved. Produced are test signatures that are stored in a memory for later comparison with standardized signatures to determine the PASS/FAIL condition of the processor. Tests can be preceded and followed by a controlled scan of the digital logic to save and restore the operational state of the digital logic. In this manner, test interruptions are relatively unobtrusive and essentially transparent to the logic tested.

摘要翻译： 公开了用于产生用于测试目的的应用于数据处理器或其它数字逻辑单元的伪随机位模式的装置。 根据本发明，数据处理器的某些元素存储单元（例如，触发器）被设计用于双模式操作：正常操作模式，其中它们以正常方式作为数据处理器的一部分操作，以及 扫描模式操作，其中元件存储单元响应于扫描控制信号以形成多个移位寄存器或扫描线配置，用于接收由该装置产生的伪随机排序或非随机排序的测试图案。 在测试期间，位模式通过扫描线配置并应用到压缩电路，其中使用循环冗余校验（CRC），实现从扫描线接收的压缩位模式。 产生的是存储在存储器中的测试签名，用于随后与标准化签名进行比较，以确定处理器的PASS / FAIL条件。 测试可以在数字逻辑之前和之后进行受控扫描，以保存和恢复数字逻辑的操作状态。 以这种方式，测试中断对于所测试的逻辑来说是相对不引人注目的并且基本上是透明的。