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85 条记录 (耗时 0.04 秒)

    Memory controller, semiconductor memory, and memory system
    1.
    发明申请
    Memory controller, semiconductor memory, and memory system 有权
    存储器控制器，半导体存储器和存储器系统

    公开(公告)号：US20070180202A1

    公开(公告)日：2007-08-02

    申请号：US11442576

    申请日：2006-05-30

    申请人： Kuninori Kawabata ,  Satoshi Eto ,  Toshiya Miyo

    发明人： Kuninori Kawabata ,  Satoshi Eto ,  Toshiya Miyo

    IPC分类号： G06F13/00

    CPC分类号： G06F13/1694 ,  G06F12/02

    摘要： A memory controller connected to memory includes: an address reception unit for receiving an address code externally input together with a command; and a command conversion unit for outputting to the memory an MRS command to change the internal settings of the memory based on the address code when the address code input together with a first command specifies an address space for which the memory is not implemented.

    摘要翻译： 连接到存储器的存储器控​​制器包括：地址接收单元，用于接收与命令一起外部输入的地址码; 以及命令转换单元，用于当与第一命令一起输入的地址代码指定未实现存储器的地址空间时，向存储器输出用于基于地址代码改变存储器的内部设置的MRS命令。

    Memory controller, semiconductor memory, and memory system
    3.
    发明授权
    Memory controller, semiconductor memory, and memory system 有权
    存储器控制器，半导体存储器和存储器系统

    公开(公告)号：US07818516B2

    公开(公告)日：2010-10-19

    申请号：US11442576

    申请日：2006-05-30

    申请人： Kuninori Kawabata ,  Satoshi Eto ,  Toshiya Miyo

    发明人： Kuninori Kawabata ,  Satoshi Eto ,  Toshiya Miyo

    IPC分类号： G06F13/00

    CPC分类号： G06F13/1694 ,  G06F12/02

    摘要： A memory controller connected to memory includes: an address reception unit for receiving an address code externally input together with a command; and a command conversion unit for outputting to the memory an MRS command to change the internal settings of the memory based on the address code when the address code input together with a first command specifies an address space for which the memory is not implemented.

    摘要翻译： 连接到存储器的存储器控​​制器包括：地址接收单元，用于接收与命令一起外部输入的地址码; 以及命令转换单元，用于当与第一命令一起输入的地址代码指定未实现存储器的地址空间时，向存储器输出用于基于地址代码改变存储器的内部设置的MRS命令。

    Semiconductor memory
    6.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US07064998B2

    公开(公告)日：2006-06-20

    申请号：US11215045

    申请日：2005-08-31

    申请人： Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo

    发明人： Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40603 ,  G11C7/22 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2281 ,  G11C2211/4061

    摘要： A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.

    摘要翻译： 定时器从接收外部接入信号测量预定时间，并且在经过预定时间之后输出接入请求信号。 外部访问信号使存储器核心执行读取操作，并且访问请求信号使得存储器核心操作。 预定时间被设定为比存储器芯执行单次操作的核心操作时间长。 因此，当外部访问信号在比预定时间短的时间内变化时，存储器核不执行操作。 因此，即使当存储器核心不能正常操作的间隔提供外部访问信号时，也可以防止存储器芯故障并保留其中的数据崩溃。

    Memory system and semiconductor memory device
    9.
    发明申请
    Memory system and semiconductor memory device 审中-公开
    存储系统和半导体存储器件

    公开(公告)号：US20060136800A1

    公开(公告)日：2006-06-22

    申请号：US11088940

    申请日：2005-03-25

    申请人： Kuninori Kawabata ,  Satoshi Eto ,  Yasuhiro Onishi ,  Akira Kikutake

    发明人： Kuninori Kawabata ,  Satoshi Eto ,  Yasuhiro Onishi ,  Akira Kikutake

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1012

    摘要： A memory system that can enhance yield without increasing the chip size and without degrading the access time. A single-bit error determination circuit references parity bits required to configure a code capable of correcting a single-bit error, and determines a single-bit error to be corrected; and a double-bit error detection circuit references one redundant bit added to the parity bits, detects a double-bit error, and enables or disables the double-bit error detection in accordance with a selection signal.

    摘要翻译： 一种可以在不增加芯片尺寸并且不降低访问时间的情况下提高产量的存储系统。 单位错误确定电路参考配置能够校正单位错误的代码所需的奇偶校验位，并确定要纠正的单位错误; 并且双位错误检测电路参考添加到奇偶校验位的一个冗余位，检测双位错误，并且根据选择信号启用或禁用双位错误检测。

    Semiconductor memory device capable of driving non-selected word lines to first and second potentials
    10.
    发明申请
    Semiconductor memory device capable of driving non-selected word lines to first and second potentials 失效
    能够将未选择的字线驱动到第一和第二电位的半导体存储器件

    公开(公告)号：US20060098523A1

    公开(公告)日：2006-05-11

    申请号：US11313963

    申请日：2005-12-22

    申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

    发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

    IPC分类号： G11C8/00

    CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

    摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

    摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。