公开(公告)号：US08428137B2

公开(公告)日：2013-04-23

申请号：US12675792

申请日：2008-09-12

Applicant: Koyo Nitta ,  Hiroe Iwasaki ,  Jirou Naganuma

Inventor： Koyo Nitta ,  Hiroe Iwasaki ,  Jirou Naganuma

IPC: H04B1/66

CPC classification number: H04N19/433 ,  H04N19/436 ,  H04N19/61

Abstract: In motion search using a PE array, a technique is provided for enabling high-speed calculation while avoiding bank conflict without increasing a memory for storing pixels outside the screen. When pieces of pixel data of a plurality of lines to be read from the memory 3 (reference image memory 30) exist in a same bank, the conflict bank anticipatory read control unit 10 reads pixel data of a line in advance, and a read data holding circuit 20 holds the data until timing for inputting to a PE array unit 4. Accordingly, bank conflict can be avoided when reading pixel data from the memory 3, so that smooth pipeline processing by the PE array unit 4 can be realized.

Abstract translation: 在使用PE阵列的运动搜索中，提供了一种技术，用于在不增加用于存储屏幕外的像素的存储器的同时避免存储体冲突的同时实现高速计算。 当存储器3（参考图像存储器30）中要读取的多条行的像素数据存在于同一个存储体中时，冲突库预测读取控制单元10预先读取行的像素数据和读取数据 保持电路20保持数据直到用于输入到PE阵列单元4的定时。因此，当从存储器3读取像素数据时，可以避免存储体冲突，从而可以实现PE阵列单元4的平滑流水线处理。

公开(公告)号：US20100215105A1

公开(公告)日：2010-08-26

申请号：US12675792

申请日：2008-09-12

Applicant: Koyo Nitta ,  Hiroe Iwasaki ,  Jirou Naganuma

Inventor： Koyo Nitta ,  Hiroe Iwasaki ,  Jirou Naganuma

IPC: H04N7/26 ,  H04N7/32

CPC classification number: H04N19/433 ,  H04N19/436 ,  H04N19/61

Abstract: In motion search using a PE array, a technique is provided for enabling high-speed calculation while avoiding bank conflict without increasing a memory for storing pixels outside the screen. When pieces of pixel data of a plurality of lines to be read from the memory 3 (reference image memory 30) exist in a same bank, the conflict bank anticipatory read control unit 10 reads pixel data of a line in advance, and a read data holding circuit 20 holds the data until timing for inputting to a PE array unit 4. Accordingly, bank conflict can be avoided when reading pixel data from the memory 3, so that smooth pipeline processing by the PE array unit 4 can be realized.

Abstract translation: 在使用PE阵列的运动搜索中，提供了一种技术，用于在不增加用于存储屏幕外的像素的存储器的同时避免存储体冲突的同时实现高速计算。 当存储器3（参考图像存储器30）中要读取的多条行的像素数据存在于同一个存储体中时，冲突库预测读取控制单元10预先读取行的像素数据和读取数据 保持电路20保持数据直到用于输入到PE阵列单元4的定时。因此，当从存储器3读取像素数据时，可以避免存储体冲突，从而可以实现PE阵列单元4的平滑流水线处理。

公开(公告)号：US08902981B2

公开(公告)日：2014-12-02

申请号：US12673095

申请日：2008-08-27

Applicant: Atsushi Sagata ,  Mitsuo Ikeda ,  Hiroaki Matsuda ,  Jirou Naganuma

Inventor： Atsushi Sagata ,  Mitsuo Ikeda ,  Hiroaki Matsuda ,  Jirou Naganuma

IPC: H04N7/12 ,  H04N11/02 ,  H04N19/44 ,  H04N19/186 ,  H04N19/70 ,  H04N19/46 ,  H04N19/176 ,  H04N19/40

CPC classification number: H04N19/17 ,  H04N19/139 ,  H04N19/176 ,  H04N19/186 ,  H04N19/40 ,  H04N19/44 ,  H04N19/46 ,  H04N19/70

Abstract: A video signal generation apparatus for decoding a bit stream to generate a video signal, includes: a writing unit configured to write a flag value indicating whether a decoding target block has been coded by intra-coding or inter-coding in a specified bit position on one bit plane having a size the same as that of the decoding target block, to write information indicating a coding division form of the decoding target block in a specified common area on the one bit plane, and to write the coding information in a specified switch interpretation area on the one bit plane according to a data format conforming to the intra-coding if the decoding target block has been coded by intra-coding, and to write the coding information in the specified switch interpretation area according to a data format conforming to the inter-coding if the decoding target block has been coded by inter-coding; and a generation unit configured to generate a video signal by superimposing the one bit plane on a decoded image of the decoding target block.

Abstract translation: 一种用于解码比特流以生成视频信号的视频信号产生装置，包括：写入单元，被配置为通过帧内编码或帧间编码将指定解码目标块是否已经被编码的标志值写入指定的比特位置 具有与解码对象块的尺寸相同的一个位平面，将指示解码对象块的编码分割形式的信息写入一个位平面上的规定的公共区域，并将编码信息写入指定的开关 根据符合内部编码的数据格式，在一个位平面上的解码区域，如果解码目标块已经通过帧内编码被编码，并且根据符合以下规定的数据格式将编码信息写入指定的开关解释区域 如果解码目标块已通过帧间编码被编码，则进行编码; 以及生成单元，被配置为通过将一个比特平面叠加在解码目标块的解码图像上来生成视频信号。

公开(公告)号：US20110122948A1

公开(公告)日：2011-05-26

申请号：US12673095

申请日：2008-08-27

Applicant: Atsushi Sagata ,  Mitsuo Ikeda ,  Hiroaki Matsuda ,  Jirou Naganuma

Inventor： Atsushi Sagata ,  Mitsuo Ikeda ,  Hiroaki Matsuda ,  Jirou Naganuma

IPC: H04N11/04

CPC classification number: H04N19/17 ,  H04N19/139 ,  H04N19/176 ,  H04N19/186 ,  H04N19/40 ,  H04N19/44 ,  H04N19/46 ,  H04N19/70

Abstract: A video signal generation apparatus for decoding a bit stream to generate a video signal, includes: a writing unit configured to write a flag value indicating whether a decoding target block has been coded by intra-coding or inter-coding in a specified bit position on one bit plane having a size the same as that of the decoding target block, to write information indicating a coding division form of the decoding target block in a specified common area on the one bit plane, and to write the coding information in a specified switch interpretation area on the one bit plane according to a data format conforming to the intra-coding if the decoding target block has been coded by intra-coding, and to write the coding information in the specified switch interpretation area according to a data format conforming to the inter-coding if the decoding target block has been coded by inter-coding; and a generation unit configured to generate a video signal by superimposing the one bit plane on a decoded image of the decoding target block.

Abstract translation: 一种用于解码比特流以生成视频信号的视频信号产生装置，包括：写入单元，被配置为通过帧内编码或帧间编码将指定解码目标块是否已经被编码的标志值写入指定的比特位置 具有与解码对象块的尺寸相同的一个位平面，将指示解码对象块的编码分割形式的信息写入一个位平面上的规定的公共区域，并将编码信息写入指定的开关 根据符合内部编码的数据格式，在一个位平面上的解码区域，如果解码目标块已经通过帧内编码被编码，并且根据符合以下规定的数据格式将编码信息写入指定的开关解释区域 如果解码目标块已通过帧间编码被编码，则进行编码; 以及生成单元，被配置为通过将一个比特平面叠加在解码目标块的解码图像上来生成视频信号。