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    Non-volatile memory cell array having common drain lines and method of operating the same
    1.
    发明授权
    Non-volatile memory cell array having common drain lines and method of operating the same 失效
    具有共同漏极线的非易失性存储单元阵列及其操作方法

    公开(公告)号：US07184316B2

    公开(公告)日：2007-02-27

    申请号：US11038726

    申请日：2005-01-19

    申请人： In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

    发明人： In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0425 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

    摘要： A nonvolatile memory cell array having common drain lines and method of operating the same are disclosed. A positive voltage is applied to a gate of a selected cell and gates of memory cells that share a word line with the selected cell. A first voltage is applied to a drain of the selected cell and drains of the memory cells that share at least a drain line with the selected cell. A second voltage is applied to a source of the selected cell and sources of memory cells that share a bit line with the selected cell, the second voltage being less than the first voltage, such that electrons are injected into the charge storage region of the selected cell to program. A third voltage, which is higher than the second voltage, is applied to bit lines that are not connected to the selected cell.

    摘要翻译： 公开了一种具有共同漏极线的非易失性存储单元阵列及其操作方法。 将正电压施加到所选单元的栅极和与所选单元共享字线的存储单元的栅极。 将第一电压施加到所选择的单元的漏极和与所选择的单元共享至少漏极线的存储器单元的漏极。 将第二电压施加到所选择的单元的源和与所选择的单元共享位线的存储器单元的源，第二电压小于第一电压，使得电子被注入到所选择的单元的电荷存储区域中 单元格程序。 高于第二电压的第三电压被施加到未连接到所选择的单元的位线。

    Non-volatile memory device having a charge storage oxide layer and operation thereof
    3.
    发明申请
    Non-volatile memory device having a charge storage oxide layer and operation thereof 失效
    具有电荷存储氧化物层的非易失性存储器件及其操作

    公开(公告)号：US20050184334A1

    公开(公告)日：2005-08-25

    申请号：US11047764

    申请日：2005-02-02

    申请人： Ki-Chul Kim ,  Geum-Jong Bae ,  Byoung-jin Lee ,  Sang-Su Kim

    发明人： Ki-Chul Kim ,  Geum-Jong Bae ,  Byoung-jin Lee ,  Sang-Su Kim

    IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/792

    CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

    摘要： A non-volatile memory device includes a pair of source/drain regions disposed in a semiconductor substrate, having a channel region between them. A charge storage oxide layer is disposed on the channel region and overlaps part of each of the pair of source/drain regions. A gate electrode is disposed on the charge storage oxide layer. At least one halo implantation region is formed in the semiconductor substrate adjacent to one of the pair of source/drain regions, and overlapping the charge storage oxide layer. A program operation is performed by trapping electrons in the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed, and an erase operation is performed by injecting holes into the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed.

    摘要翻译： 非易失性存储器件包括设置在半导体衬底中的一对源极/漏极区域，它们之间具有沟道区域。 电荷存储氧化物层设置在沟道区上，并且与一对源极/漏极区的每一个的一部分重叠。 栅电极设置在电荷存储氧化物层上。 至少一个卤素注入区域形成在与一对源极/漏极区域中的一个相邻的半导体衬底中，并与电荷存储氧化物层重叠。 通过在位于形成有卤素离子注入区域的源极/漏极区附近的电荷存储氧化物层中俘获电子来执行编程操作，并且通过将空穴注入位于源/漏区附近的电荷存储氧化物层中来执行擦除操作， 漏区，其中形成有卤素离子注入区。

    Non-volatile memory device having a charge storage oxide layer and operation thereof
    4.
    发明授权
    Non-volatile memory device having a charge storage oxide layer and operation thereof 失效
    具有电荷存储氧化物层的非易失性存储器件及其操作

    公开(公告)号：US07394127B2

    公开(公告)日：2008-07-01

    申请号：US11047764

    申请日：2005-02-02

    申请人： Ki-Chul Kim ,  Geum-Jong Bae ,  Byoung-jin Lee ,  Sang-Su Kim

    发明人： Ki-Chul Kim ,  Geum-Jong Bae ,  Byoung-jin Lee ,  Sang-Su Kim

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

    摘要： A non-volatile memory device includes a pair of source/drain regions disposed in a semiconductor substrate, having a channel region between them. A charge storage oxide layer is disposed on the channel region and overlaps part of each of the pair of source/drain regions. A gate electrode is disposed on the charge storage oxide layer. At least one halo implantation region is formed in the semiconductor substrate adjacent to one of the pair of source/drain regions, and overlapping the charge storage oxide layer. A program operation is performed by trapping electrons in the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed, and an erase operation is performed by injecting holes into the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed.

    摘要翻译： 非易失性存储器件包括设置在半导体衬底中的一对源极/漏极区域，它们之间具有沟道区域。 电荷存储氧化物层设置在沟道区上，并且与一对源极/漏极区的每一个的一部分重叠。 栅电极设置在电荷存储氧化物层上。 至少一个卤素注入区域形成在与一对源极/漏极区域中的一个相邻的半导体衬底中，并与电荷存储氧化物层重叠。 通过在位于形成有卤素离子注入区域的源极/漏极区附近的电荷存储氧化物层中俘获电子来执行编程操作，并且通过将空穴注入位于源/漏区附近的电荷存储氧化物层中来执行擦除操作， 漏区，其中形成有卤素离子注入区。

    Method of forming silicon-on-insulator (SOI) semiconductor substrate and SOI semiconductor substrate formed thereby
    5.
    发明授权
    Method of forming silicon-on-insulator (SOI) semiconductor substrate and SOI semiconductor substrate formed thereby 失效
    形成绝缘体上硅（SOI）半导体衬底和由此形成的SOI半导体衬底的方法

    公开(公告)号：US07183172B2

    公开(公告)日：2007-02-27

    申请号：US10397447

    申请日：2003-03-26

    申请人： Jung-Il Lee ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Hwa-Sung Rhee ,  Sang-Su Kim

    发明人： Jung-Il Lee ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Hwa-Sung Rhee ,  Sang-Su Kim

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76259 ,  H01L21/76254

    摘要： A method of forming an SOI semiconductor substrate and the SOI semiconductor substrate formed thereby, is provided. The method includes forming sequentially buried oxide, diffusion barrier and SOI layers on a semiconductor substrate. The diffusion barrier layer is formed by an insulating layer having a lower impurity diffusion coefficient as compared with the buried oxide layer. The diffusion barrier layer serves to prevent impurities implanted into the SOI layer from being diffused into the buried oxide layer or the semiconductor substrate.

    摘要翻译： 提供了一种形成SOI半导体衬底的方法和由此形成的SOI半导体衬底。 该方法包括在半导体衬底上顺序地形成掩埋氧化物，扩散阻挡层和SOI层。 与掩埋氧化物层相比，扩散阻挡层由具有较低杂质扩散系数的绝缘层形成。 扩散阻挡层用于防止注入到SOI层中的杂质扩散到掩埋氧化物层或半导体衬底中。

    Semiconductor device with floating trap type nonvolatile memory cell and method for manufacturing the same
    7.
    发明申请
    Semiconductor device with floating trap type nonvolatile memory cell and method for manufacturing the same 失效
    具有浮动阱型非易失性存储单元的半导体器件及其制造方法

    公开(公告)号：US20060208303A1

    公开(公告)日：2006-09-21

    申请号：US11378505

    申请日：2006-03-17

    申请人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

    发明人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

    摘要： The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

    摘要翻译： 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 顺序地形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层组成的三层。 然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。

    Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturing the same
    8.
    发明授权
    Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturing the same 失效
    具有两片门和自对准ONO的本地SONOS型结构及其制造方法

    公开(公告)号：US07060563B2

    公开(公告)日：2006-06-13

    申请号：US10953553

    申请日：2004-09-30

    申请人： Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

    发明人： Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

    IPC分类号： H01L21/8247

    CPC分类号： H01L29/792 ,  H01L29/7923 ,  Y10S438/954

    摘要： A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.

    摘要翻译： 具有两件式门和自对准ONO结构的本地SONOS结构包括：衬底; 基底上的ONO结构; 在ONO结构上并与ONO结构对准的第一栅极层; 衬底上的栅极绝缘体旁边的ONO结构; 以及在第一栅极层上和栅极绝缘体上的第二栅极层。 第一和第二栅极层电连接在一起。 ONO结构和第一和第二栅极层一起定义至少1位本地SONOS结构。 相应的制造方法包括：提供衬底; 在基板上形成ONO结构; 在ONO结构上形成第一栅极层并与其结合; 在衬底上形成栅极绝缘体，除了ONO结构; 在第一栅极层和栅极绝缘体上形成第二栅极层; 并且电连接第一和第二栅极层。

    Method of manufacturing a non-volatile semiconductor memory device
    9.
    发明授权
    Method of manufacturing a non-volatile semiconductor memory device 有权
    制造非易失性半导体存储器件的方法

    公开(公告)号：US06998309B2

    公开(公告)日：2006-02-14

    申请号：US10786239

    申请日：2004-02-24

    申请人： In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

    发明人： In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11568 ,  Y10S438/954

    摘要： A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.

    摘要翻译： 制造非易失性半导体存储器件的方法是通过在衬底上形成具有ONO组成的电介质层图案而开始的。 在包括在电介质层图案上的衬底上形成多晶硅层。 图案化多晶硅层以形成暴露部分介电层图案的分裂多晶硅层图案。 暴露的电介质层被蚀刻，然后使用分离多晶硅层图案作为掩模将杂质注入到衬底的部分中，从而在衬底中形成具有垂直轮廓的源区。

    Semiconductor device with floating trap type nonvolatile memory cell and method for manufacturing the same
    10.
    发明申请
    Semiconductor device with floating trap type nonvolatile memory cell and method for manufacturing the same 有权
    具有浮动阱型非易失性存储单元的半导体器件及其制造方法

    公开(公告)号：US20050023604A1

    公开(公告)日：2005-02-03

    申请号：US10844783

    申请日：2004-05-13

    申请人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

    发明人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

    IPC分类号： H01L21/8234 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/788

    CPC分类号： H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

    摘要： The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

    摘要翻译： 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 顺序地形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层组成的三层。 然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。