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公开(公告)号：US4253187A
公开(公告)日：1981-02-24
申请号：US28710
申请日：1979-04-10
IPC分类号： G11B27/28 , G11B20/14 , G11B27/32 , H04L7/00 , H04L7/033 , H04L25/38 , H04L25/48 , H04N5/78 , H04L27/18 , H04L7/02
CPC分类号： G11B20/1403 , G11B20/1419 , G11B27/323
摘要： A first self-timing signal bi-phase-mark coded and having a data portion and a synchronization portion is to be sequenced by a second signal also having a data and a synchronization portion. The signals derived by differentiating only the level change at the end of each bit cell phase-lock an oscillator whose output provides the basic timing for a modulator stage. In the modulator stage, a flip-flop first changes state under control of the first signal. At the start of the synchronization portion of the first signal, a comparator furnishes a signal which switches control of the flip-flop to signals derived from differentiation of the second signal. When the second signal is binary coded, a NAND gate modulates the pulses from the second signal by pulses resulting from differentiating negative going edges of the signal derived from the phase-locked oscillator to create a signal for controlling the flip-flop so that it changes state in accordance with a bi-phase-mark code.
摘要翻译： 编码并具有数据部分和同步部分的第一自定时信号双相标记将被也具有数据和同步部分的第二信号排序。 通过仅区分每个比特单元结束时的电平变化而导出的信号锁相其输出提供调制器级的基本定时的振荡器。 在调制器级中，触发器首先在第一信号的控制下改变状态。 在第一信号的同步部分开始时，比较器提供将触发器的控制切换到从第二信号的微分导出的信号的信号。 当第二信号被二进制编码时，NAND门通过由从锁相振荡器导出的信号的差分负向边沿产生的脉冲从第二信号中调制脉冲，以产生用于控制触发器的信号，使得其改变 状态按照双相标记代码。
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公开(公告)号：US4599736A
公开(公告)日：1986-07-08
申请号：US632582
申请日：1984-07-19
申请人： Karl-Heinz Hoppe
发明人： Karl-Heinz Hoppe
CPC分类号： H04L25/4904 , G11B20/1419 , H03K5/1565
摘要： A wide band constant duty cycle pulse train processing circuit where the pulse train frequency varies is proposed. The circuit serves primarily to obtain the basic clock in decoding signals encoded in the bi-phase mark code and includes a pulse-shaping or wave-shaping circuit, which receives the data signals and is followed by a low-pass filter; a differential amplifier circuit, one input of which is connected to the output of the low-pass filter and the other input of which is connected to a variable voltage source; and a current source, controlled by the differential amplifier circuit, at the input of the wave-shaping circuit determining the pulse length. The closed control loop between the output and the input of the wave-shaping circuit that determines the pulse length causes the duty cycle established at the variable voltage source to be maintained over wide ranges of the incident pulse train frequency.
摘要翻译： 提出了脉冲串频率变化的宽带恒定占空比脉冲串处理电路。 该电路主要用于获得编码在双相标记码中的信号的解码中的基本时钟，并且包括脉冲整形或波形整形电路，其接收数据信号并且后跟低通滤波器; 差分放大器电路，其一个输入端连接到低通滤波器的输出端，另一个输入端连接到可变电压源; 以及由差分放大器电路控制的电流源，在波形整形电路的输入端确定脉冲长度。 确定脉冲长度的波形整形电路的输出和输入端之间的闭合控制环路使可变电压源上建立的占空比保持在入射脉冲序列频率的宽范围内。
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公开(公告)号：US4353091A
公开(公告)日：1982-10-05
申请号：US216862
申请日：1980-12-16
申请人： Karl-Heinz Hoppe
发明人： Karl-Heinz Hoppe
IPC分类号： H03K5/00 , H03K5/1252 , H04B1/10 , H04N5/08 , H04N5/213 , H04N7/02 , H03K5/18 , H04N5/04 , H04N7/04
CPC分类号： H03K5/00 , H03K5/1252 , H04B1/10 , H04N5/08 , H04N5/213
摘要： To obtain a switching signal whenever a fault occurs in the synchronization signals of a video signal, a fault detection circuit has a counter which receives the signals to be tested at its clock input and reference signals at its control input. The reference signals have the same pulse frequency as the signals to be tested and are obtained from the signals to be tested by a change in keying ratio. The output of the counter is connected in its "clear" input and also, via a monostable flip-flop, to an input from an OR-gate. The other input of the OR-gate receives the reference signals via a diode and an RC-link. The desired switching signal is obtained at the output of the OR-gate.
摘要翻译： 为了在视频信号的同步信号中发生故障时获得切换信号，故障检测电路具有在其时钟输入端接收要测试的信号的计数器和其控制输入端的参考信号。 参考信号具有与要测试的信号相同的脉冲频率，并且通过键控比的变化从要测试的信号获得。 计数器的输出连接在其“清零”输入端，并通过单稳态触发器连接到或门的输入。 OR门的另一个输入端通过二极管和RC链路接收参考信号。 在OR门的输出端获得所需的开关信号。
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