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    Low-power and all-digital phase interpolator-based clock and data recovery architecture
    2.
    发明授权
    Low-power and all-digital phase interpolator-based clock and data recovery architecture 有权
    基于低功耗和全数字相位插值器的时钟和数据恢复架构

    公开(公告)号：US09166605B2

    公开(公告)日：2015-10-20

    申请号：US13846688

    申请日：2013-03-18

    Applicant: Korea Advanced Institute of Science and Technology

    Inventor： Hyeon Min Bae ,  Tae Hun Yoon ,  Joon Yeong Lee

    IPC: H03L7/00 ,  H03L7/081 ,  H04J3/06 ,  H03L7/07 ,  H03L7/099

    CPC classification number: H03L7/081 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0998 ,  H04J3/06

    Abstract: The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)-based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jitter-tolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for low-power applications since a phase shifter in the data path, which is one of the most power-hungry blocks in conventional DPLL designs, is not required.

    Abstract translation: 所提出的发明是关于串行和串行收发器应用的改进方法。 所提出的系统包括具有PLL和基于相位旋转器（PR）的延迟锁定环（DLL）的双环路锁相环（PLL）架构。 该架构的优点是单个PLL提供去耦带宽; 用于接收数据的宽抖动容限（JTOL）带宽和用于数据传输的窄抖动传输（JTRAN）带宽。 因此，在提供足够的抖动跟踪带宽的同时，输出端的抖动量可以相对于输入显着减小。 此外，该架构适用于低功耗应用，因为数据路径中的移相器是传统DPLL设计中功耗最大的块之一。

    Low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters
    3.
    发明授权
    Low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters 有权
    低功耗高精度无源多相时钟生成方案采用多相滤波器

    公开(公告)号：US08774336B2

    公开(公告)日：2014-07-08

    申请号：US13833407

    申请日：2013-03-15

    Applicant: Korea Advanced Institute of Science and Technology ,  TeraSquare Co., Ltd.

    Inventor： Hyeon Min Bae ,  Hyo Sup Won ,  Joon Yeong Lee ,  Jin Ho Park ,  Tae Ho Kim

    IPC: H04L7/00 ,  H04L7/02

    CPC classification number: H04L7/00 ,  H03L7/0807 ,  H03L7/0814 ,  H04L7/0337

    Abstract: Exemplary embodiments of the present invention relate to a low-power highly-accurate passive multiphase clock generation scheme by using polyphase filters. An exemplary embodiment of the present invention may be low power phase-rotator-based 25 GB/s CDR architecture in case that half-rate reference clock is provided. It may be suitable for multi-lane scheme and incorporate phase interpolator with improved phase accuracy to make Nyquist-sampling clock phase. To improve the phase accuracy, poly phase filter may be used for converting 4-phase to 8-phase and interpolate adjacent 45 degree different phases. The linearity of phase rotator may be improved by proposed harmonic rejection poly phase filter (HRPPF) using the characteristic of notch filter response.

    Abstract translation: 本发明的示例性实施例涉及通过使用多相滤波器的低功率高精度无源多相时钟生成方案。 在提供半速率参考时钟的情况下，本发明的示例性实施例可以是基于低功率相位旋转器的25GB / s CDR架构。 它可能适用于多通道方案，并且并入具有提高的相位精度的相位内插器，以使奈奎斯特采样时钟相位。 为了提高相位精度，多相滤波器可用于将4相转换为8相，并内插相邻的45度相位。 通过使用陷波滤波器响应的特性，提出的谐波抑制多相滤波器（HRPPF）可以改善相位旋转器的线性度。

    Low power, high speed multi-channel chip-to-chip interface using dielectric waveguide
    6.
    发明授权
    Low power, high speed multi-channel chip-to-chip interface using dielectric waveguide 有权
    低功率，高速多通道芯片到芯片接口采用介质波导

    公开(公告)号：US09093732B2

    公开(公告)日：2015-07-28

    申请号：US14103005

    申请日：2013-12-11

    Applicant: Korea Advanced Institute of Science and Technology

    Inventor： Hyeon Min Bae ,  Ha Il Song ,  Huxian Jin

    IPC: H01P3/12 ,  H01P3/16 ,  H01P5/08 ,  H01P5/107

    CPC classification number: H01P3/122 ,  H01P3/16 ,  H01P5/087 ,  H01P5/107

    Abstract: An exemplary embodiment of the present invention provides an improved dielectric waveguide named electrical fiber. The electrical fiber with a metal cladding may isolate the interference of the signals in other wireless channels and adjacent electrical fibers, which typically causes band-limitation problem, for a smaller radiation loss and better signal guiding to lower the total transceiver power consumption as the transmit distance increases. Also, the electrical fiber may have frequency independent attenuation characteristics to enable high data rate transfer with little or even without any additional receiver-side compensation due to vertical coupling of the electrical fiber and an interconnection device.

    Abstract translation: 本发明的示例性实施例提供了一种改进的电介质波导，称为电光纤。 具有金属覆层的电光纤可以隔离其它无线信道和相邻电缆中的信号的干扰，这通常导致带限问题，以减小辐射损耗，并且更好的信号导向以降低总的收发机功率消耗，因为传输 距离增加。 此外，电光纤可以具有频率独立的衰减特性，以便由于电光纤和互连设备的垂直耦合而很少或甚至没有任何额外的接收器侧补偿来实现高数据速率传输。

    Efficient data extraction method for high-temporal-and-spatial-resolution near infrared spectroscopy system
    7.
    发明授权
    Efficient data extraction method for high-temporal-and-spatial-resolution near infrared spectroscopy system 有权
    高分辨率近红外光谱系统的高效数据提取方法

    公开(公告)号：US09040917B2

    公开(公告)日：2015-05-26

    申请号：US13744339

    申请日：2013-01-17

    Applicant: Korea Advanced Institute of Science and Technology

    Inventor： Hyeon Min Bae ,  Jong-Kwan Choi ,  Min-Gyu Choi

    IPC: G01J5/02 ,  G01J3/28 ,  A61B5/1455 ,  G01N21/359

    CPC classification number: G01J3/28 ,  A61B5/0042 ,  A61B5/14553 ,  G01N21/359

    Abstract: An efficient method for the extraction of hemodynamic responses in Near-Infrared Spectroscopy (NIRS) systems is proposed to increase the spatial and temporal resolution without hardware overhead. The performance improvement is attributed to high Signal-to-Noise-Ratio (SNR) receivers, a modulation scheme, and a Multi-Input-Multi-Output (MIMO) based data extraction algorithm. The proposed system shows an over 2× increment in the figure of merit (FOM) compared to conventional designs. Experimental results support the validity of the proposed system.

    Abstract translation: 提出了一种在近红外光谱（NIRS）系统中提取血液动力学反应的有效方法，以增加空间和时间分辨率，而无需硬件开销。 性能改进归因于高信噪比（SNR）接收机，调制方案和基于多输入多输出（MIMO）的数据提取算法。 与常规设计相比，所提出的系统显示出超过2倍的品质因数（FOM）。 实验结果支持拟议系统的有效性。

    LOW-POWER CML-LESS TRANSMITTER ARCHITECTURE
    8.
    发明申请
    LOW-POWER CML-LESS TRANSMITTER ARCHITECTURE 有权
    低功耗CML-LESS发射机架构

    公开(公告)号：US20140269761A1

    公开(公告)日：2014-09-18

    申请号：US13835530

    申请日：2013-03-15

    Applicant: Korea Advanced Institute of Science and Technology ,  TERASQUARE CO., LTD.

    Inventor： Hyeon Min Bae ,  Tae Hun Yoon ,  Jin Ho Park ,  Tae Ho Kim

    IPC: H04J3/04

    CPC classification number: H04J3/04 ,  H03K19/1737 ,  H04L25/0286

    Abstract: Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.

    Abstract translation: 本发明的示例性实施例涉及低功率电流模式逻辑（CML）无发射机架构。 发射机包括：主多路复用器，被配置为通过将从重定时器重新定时的并行主数据信号复用在并行输入数据信号之间的时间间隔和来自时钟分配器的多相时钟信号之间产生主数据信号，辅复用器被配置为生成后数据 通过复原从重定时器重新定时的并行后数据信号的多个输出驱动器，以及配置成通过对主数据信号和后数据信号求和来产生串行数据信号的多个输出驱动器。

    PHASE INTERPOLATOR BASED OUTPUT WAVEFORM SYNTHESIZER FOR LOW-POWER BROADBAND TRANSMITTER
    9.
    发明申请
    PHASE INTERPOLATOR BASED OUTPUT WAVEFORM SYNTHESIZER FOR LOW-POWER BROADBAND TRANSMITTER 有权
    用于低功率宽带发射器的基于相位插值器的输出波形合成器

    公开(公告)号：US20140266318A1

    公开(公告)日：2014-09-18

    申请号：US13843054

    申请日：2013-03-15

    Applicant: Korea Advanced Institute of Science and Technology

    Inventor： Hyeon Min Bae ,  Tae Hun Yoon ,  Jong Hyeok Yoon

    IPC: H03B21/00

    CPC classification number: H03B21/00 ,  H03K5/1536 ,  H03M9/00 ,  H04L7/0332

    Abstract: Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed.

    Abstract translation: 本发明的示例性实施例涉及一种使用相位内插器的输出波形合成器和用于低功率发射器的片上开眼监测（EOM）电路。 为了在发射机设计中实现小面积和低功耗，采用了以子速率工作的单级多相多路复用器。 多相多路复用器由并联开漏NAND门组成。 在子速率发射机架构中，多相时钟信号之间的相位不匹配会显着降低抖动性能，并且是低功耗的广泛使用的关键瓶颈。 为了克服这种不匹配问题，开发了基于面积和功率的相位插值器的波形合成方案。

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