公开(公告)号：US20140266318A1

公开(公告)日：2014-09-18

申请号：US13843054

申请日：2013-03-15

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Hyeon Min Bae ,  Tae Hun Yoon ,  Jong Hyeok Yoon

IPC: H03B21/00

CPC classification number: H03B21/00 ,  H03K5/1536 ,  H03M9/00 ,  H04L7/0332

Abstract: Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed.

Abstract translation: 本发明的示例性实施例涉及一种使用相位内插器的输出波形合成器和用于低功率发射器的片上开眼监测（EOM）电路。 为了在发射机设计中实现小面积和低功耗，采用了以子速率工作的单级多相多路复用器。 多相多路复用器由并联开漏NAND门组成。 在子速率发射机架构中，多相时钟信号之间的相位不匹配会显着降低抖动性能，并且是低功耗的广泛使用的关键瓶颈。 为了克服这种不匹配问题，开发了基于面积和功率的相位插值器的波形合成方案。

公开(公告)号：US08938043B2

公开(公告)日：2015-01-20

申请号：US13833321

申请日：2013-03-15

Applicant: Korea Advanced Institute of Science and Technology ,  TeraSquare Co., Ltd.

Inventor： Hyeon Min Bae ,  Joon Yeong Lee ,  Hyo Sup Won ,  Jong Hyeok Yoon ,  Jin Ho Park ,  Tae Ho Kim

IPC: H03D3/24 ,  H04L27/00 ,  H04L7/00 ,  H04L7/033

CPC classification number: H04L7/007 ,  H04L7/0331

Abstract: Exemplary embodiments of the present invention relate to a clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor. The Kalman gain extractor includes an off chip digital processor which receives a phase update information from the CDR outputs an estimated optimum Kalman gain obtained by extracting the standard deviation of step sizes of the accumulation jitter from the power spectral density (PSD) of the phase update information, and a on chip digital loop filter consists of a cyclic accumulator which accumulates the phase detector's output, a gain multiplier and a phase interpolator (or DCO) controller. The off chip digital processor includes a storage register, a fast Fourier transform (FFT) processor and an optimum Kalman gain estimator. The storage register stores the phase update information, from which the FFT processor extracts the PSD of the absolute input jitter. The optimum Kalman gain estimator calculates the optimum gain from the PSD of the accumulation jitter. The off chip digital processor may further include a gain calibrator to compensate for the variations in the transition density.

Abstract translation: 本发明的示例性实施例涉及通过使用卡尔曼增益提取器具有自适应最佳CDR带宽估计的时钟和数据恢复（CDR）装置。 卡尔曼增益提取器包括离线数字处理器，其接收来自CDR的相位更新信息，输出通过从相位更新的功率谱密度（PSD）提取积累抖动的步长的标准偏差而获得的估计的最佳卡尔曼增益 信息和片上数字环路滤波器由积累相位检测器输出的循环累加器，增益乘法器和相位内插器（或DCO）控制器组成。 片外数字处理器包括存储寄存器，快速傅里叶变换（FFT）处理器和最佳卡尔曼增益估计器。 存储寄存器存储相位更新信息，FFT处理器从该存储器提取绝对输入抖动的PSD。 最佳卡尔曼增益估计器从累积抖动的PSD计算最佳增益。 片外数字处理器还可以包括增益校准器，以补偿转换密度的变化。

公开(公告)号：US20130259178A1

公开(公告)日：2013-10-03

申请号：US13833321

申请日：2013-03-15

Applicant: Korea Advanced Institute of Science and Technology ,  TERASQUARE CO., LTD.

Inventor： Hyeon Min Bae ,  Joon Young Lee ,  Hyo Sup Won ,  Jong Hyeok Yoon ,  Jin Ho Park ,  Tae Ho Kim

IPC: H04L7/00

CPC classification number: H04L7/007 ,  H04L7/0331

Abstract: Exemplary embodiments of the present invention relate to a clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor. The Kalman gain extractor includes an off chip digital processor which receives a phase update information from the CDR outputs an estimated optimum Kalman gain obtained by extracting the standard deviation of step sizes of the accumulation jitter from the power spectral density (PSD) of the phase update information, and a on chip digital loop filter consists of a cyclic accumulator which accumulates the phase detector's output, a gain multiplier and a phase interpolator (or DCO) controller. The off chip digital processor includes a storage register, a fast Fourier transform (FFT) processor and an optimum Kalman gain estimator. The storage register stores the phase update information, from which the FFT processor extracts the PSD of the absolute input jitter. The optimum Kalman gain estimator calculates the optimum gain from the PSD of the accumulation jitter. The off chip digital processor may further include a gain calibrator to compensate for the variations in the transition density.

Abstract translation: 本发明的示例性实施例涉及通过使用卡尔曼增益提取器具有自适应最佳CDR带宽估计的时钟和数据恢复（CDR）装置。 卡尔曼增益提取器包括离线数字处理器，其接收来自CDR的相位更新信息，输出通过从相位更新的功率谱密度（PSD）提取积累抖动的步长的标准偏差而获得的估计的最佳卡尔曼增益 信息和片上数字环路滤波器由积累相位检测器输出的循环累加器，增益乘法器和相位内插器（或DCO）控制器组成。 片外数字处理器包括存储寄存器，快速傅里叶变换（FFT）处理器和最佳卡尔曼增益估计器。 存储寄存器存储相位更新信息，FFT处理器从该存储器提取绝对输入抖动的PSD。 最佳卡尔曼增益估计器从累积抖动的PSD计算最佳增益。 片外数字处理器还可以包括增益校准器，以补偿转换密度的变化。