Method for Reducing Wafer Shape and Thickness Measurement Errors Resulted From Cavity Shape Changes
    1.
    发明申请
    Method for Reducing Wafer Shape and Thickness Measurement Errors Resulted From Cavity Shape Changes 有权
    降低由形状变化导致的晶圆形状和厚度测量误差的方法

    公开(公告)号:US20130182262A1

    公开(公告)日:2013-07-18

    申请号:US13742113

    申请日:2013-01-15

    CPC classification number: G01B9/02076 G01B9/02027

    Abstract: Methods and systems for reducing wafer shape and thickness measurement errors resulted from cavity shape changes are disclosed. Cavity calibration process is performed immediately before the wafer measurement. Calibrating the cavity characteristics every time the method is executed reduces wafer shape and thickness measurement errors resulted from cavity shape changes. Additionally or alternatively, a polynomial fitting process utilizing a polynomial of at least a second order is utilized for cavity tilt estimation. High order cavity shape information generated using high order polynomials takes into consideration cavity shape changes due to temperature variations, stress or the like, effectively increases accuracy of the wafer shape and thickness information computed.

    Abstract translation: 公开了用于减小由腔形变化导致的晶片形状和厚度测量误差的方法和系统。 在晶片测量之前立即进行腔校准处理。 每次执行该方法时校准腔体特性可降低由腔体形状变化导致的晶片形状和厚度测量误差。 附加地或替代地,利用至少二阶多项式的多项式拟合过程用于腔倾斜估计。 使用高阶多项式生成的高阶腔形状信息考虑到由于温度变化,应力等引起的空腔形状变化,有效地提高了计算出的晶片形状和厚度信息的精度。

    Reducing registration error of front and back wafer surfaces utilizing a see-through calibration wafer
    4.
    发明授权
    Reducing registration error of front and back wafer surfaces utilizing a see-through calibration wafer 有权
    使用透视校准晶圆减少前后晶片表面的配准误差

    公开(公告)号:US09163928B2

    公开(公告)日:2015-10-20

    申请号:US13864701

    申请日:2013-04-17

    Abstract: A calibration wafer and a method for calibrating an interferometer system are disclosed. The calibration method includes: determining locations of the holes defined in the calibration wafer based on two opposite intensity frame; comparing the locations of the holes against the locations measured utilizing an external measurement device; adjusting a first optical magnification or a second optical magnification at least partially based on the comparison result; defining a distortion map for each of the first and second intensity frames based on the comparison of the locations of the holes; generating an extended distortion map for each of the first and second intensity frames by map fitting the distortion map; and utilizing the extended distortion map for each of the first and second intensity frames to reduce at least one of: a registration error or an optical distortion in a subsequent measurement process.

    Abstract translation: 公开了一种用于校准干涉仪系统的校准晶片和方法。 校准方法包括:基于两个相对强度的帧确定校准晶片中限定的孔的位置; 比较孔的位置与使用外部测量装置测量的位置; 至少部分地基于比较结果调整第一光学倍率或第二光学倍率; 基于孔的位置的比较来定义第一和第二强度帧中的每一个的失真图; 通过映射拟合失真图来生成第一和第二强度帧中的每一个的扩展失真图; 以及利用所述第一和第二强度帧中的每一个的所述扩展失真图来减少随后测量过程中的注册误差或光学失真中的至少一个。

    Method for reducing wafer shape and thickness measurement errors resulted from cavity shape changes
    5.
    发明授权
    Method for reducing wafer shape and thickness measurement errors resulted from cavity shape changes 有权
    降低晶体形状和厚度测量误差的方法是由腔形变化引起的

    公开(公告)号:US09121684B2

    公开(公告)日:2015-09-01

    申请号:US13742113

    申请日:2013-01-15

    CPC classification number: G01B9/02076 G01B9/02027

    Abstract: Methods and systems for reducing wafer shape and thickness measurement errors resulted from cavity shape changes are disclosed. Cavity calibration process is performed immediately before the wafer measurement. Calibrating the cavity characteristics every time the method is executed reduces wafer shape and thickness measurement errors resulted from cavity shape changes. Additionally or alternatively, a polynomial fitting process utilizing a polynomial of at least a second order is utilized for cavity tilt estimation. High order cavity shape information generated using high order polynomials takes into consideration cavity shape changes due to temperature variations, stress or the like, effectively increases accuracy of the wafer shape and thickness information computed.

    Abstract translation: 公开了用于减小由腔形变化导致的晶片形状和厚度测量误差的方法和系统。 在晶片测量之前立即进行腔校准处理。 每次执行该方法时校准腔体特性可降低由腔体形状变化导致的晶片形状和厚度测量误差。 附加地或替代地,利用至少二阶多项式的多项式拟合过程用于腔倾斜估计。 使用高阶多项式生成的高阶腔形状信息考虑到由于温度变化,应力等引起的空腔形状变化,有效地提高了计算出的晶片形状和厚度信息的精度。

    Reducing Registration Error of Front and Back Wafer Surfaces Utilizing a See-Through Calibration Wafer
    6.
    发明申请
    Reducing Registration Error of Front and Back Wafer Surfaces Utilizing a See-Through Calibration Wafer 有权
    使用透视校准晶圆减少前后晶片表面的配准误差

    公开(公告)号:US20140313516A1

    公开(公告)日:2014-10-23

    申请号:US13864701

    申请日:2013-04-17

    Abstract: A calibration wafer and a method for calibrating an interferometer system are disclosed. The calibration method includes: determining locations of the holes defined in the calibration wafer based on two opposite intensity frame; comparing the locations of the holes against the locations measured utilizing an external measurement device; adjusting a first optical magnification or a second optical magnification at least partially based on the comparison result; defining a distortion map for each of the first and second intensity frames based on the comparison of the locations of the holes; generating an extended distortion map for each of the first and second intensity frames by map fitting the distortion map; and utilizing the extended distortion map for each of the first and second intensity frames to reduce at least one of: a registration error or an optical distortion in a subsequent measurement process.

    Abstract translation: 公开了一种用于校准干涉仪系统的校准晶片和方法。 校准方法包括:基于两个相对强度的帧确定校准晶片中限定的孔的位置; 比较孔的位置与使用外部测量装置测量的位置; 至少部分地基于比较结果调整第一光学倍率或第二光学倍率; 基于孔的位置的比较来定义第一和第二强度帧中的每一个的失真图; 通过映射拟合失真图来生成第一和第二强度帧中的每一个的扩展失真图; 以及利用所述第一和第二强度帧中的每一个的所述扩展失真图来减少随后测量过程中的注册误差或光学失真中的至少一个。

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