公开(公告)号：US20170110186A1

公开(公告)日：2017-04-20

申请号：US15530248

申请日：2016-12-16

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Takahiko Sasaki ,  Go Shikata ,  Tomonori Kurosawa ,  Rieko Funatsuki

IPC分类号： G11C11/56 ,  G11C16/32 ,  G11C16/34

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/32 ,  G11C16/3459

摘要： According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, first and second bit lines, a sense amplifier and a driver. The first and second memory cells have first and second threshold voltages, respectively. The word line is electrically connected to the first and second memory cells. The first and second bit lines are electrically connected to the first and second memory cells, respectively. The driver increases gradually the voltage of the word line. When the voltage of the word line is increased gradually by the driver, the sense amplifier senses the first and second threshold voltages in ascending order.

公开(公告)号：US09305637B2

公开(公告)日：2016-04-05

申请号：US14194781

申请日：2014-03-02

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Rieko Funatsuki ,  Takuya Futatsuyama ,  Fumitaka Arai

IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3431 ,  G11C16/3459

摘要： A nonvolatile semiconductor memory device includes a memory cell array having nonvolatile memory cells in which one of multiple values is programmable therein by setting one of a plurality of threshold values therein and a control circuit that performs a writing operation on the memory cells. The writing operation performed by the control circuit includes a pre-programming verification operation to determine a threshold level of a memory cell in an erasure state, and a program operation in which a program voltage is selected from a plurality of program voltages on the basis of a determination result of the pre-programming verification operation.

摘要翻译： 非易失性半导体存储器件包括具有非易失性存储器单元的存储单元阵列，其中多个值中的一个可通过设置多个阈值中的一个来编程，以及对存储单元执行写入操作的控制电路。 由控制电路执行的写入操作包括用于确定擦除状态下的存储单元的阈值电平的预编程验证操作，以及基于从多个编程电压选择编程电压的编程操作 预编程验证操作的确定结果。

公开(公告)号：US08830760B2

公开(公告)日：2014-09-09

申请号：US13771328

申请日：2013-02-20

申请人： Kabushiki Kaisha Toshiba

发明人： Rieko Funatsuki ,  Osamu Nagao

IPC分类号： G11C16/06 ,  G11C16/34 ,  G11C16/28 ,  G11C7/14

CPC分类号： G11C16/3459 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/28

摘要： A memory includes memory cells and a sense amplifier including a sense node that transmits a voltage according to a current flowing in one of the memory cells and detects logic of data based on the voltage of the sense node. A write sequence of writing data in a selected cell is performed by repeating write loops each including a write stage of writing data in the selected cell and a verify read stage of verifying that the data has been written in the selected cell by performing discharge from the sense node through the selected cell. The sense amplifier changes, according to a logic of data detected at the verify read stage in a first write loop, a period of discharge from the sense node to the selected cell at the verify read stage in a second write loop following the first write loop.

摘要翻译： 存储器包括存储器单元和包括感测节点的读出放大器，该感测放大器根据在一个存储器单元中流动的电流传输电压，并且基于感测节点的电压来检测数据的逻辑。 通过重复写入循环来执行所选单元中的写入数据的写入序列，每个写入循环包括在所选择的单元中写入数据的写入级，以及通过执行从所选单元中的放电来验证数据已被写入所选择的单元的验证读取级 通过选定的单元感知节点。 读出放大器根据在第一写入循环中的验证读取阶段检测到的数据的逻辑，在第一写入循环之后的第二写入循环中在验证读取阶段从检测节点到所选择的单元的放电周期发生变化 。