公开(公告)号：US20170110186A1

公开(公告)日：2017-04-20

申请号：US15530248

申请日：2016-12-16

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Takahiko Sasaki ,  Go Shikata ,  Tomonori Kurosawa ,  Rieko Funatsuki

IPC分类号： G11C11/56 ,  G11C16/32 ,  G11C16/34

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/32 ,  G11C16/3459

摘要： According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, first and second bit lines, a sense amplifier and a driver. The first and second memory cells have first and second threshold voltages, respectively. The word line is electrically connected to the first and second memory cells. The first and second bit lines are electrically connected to the first and second memory cells, respectively. The driver increases gradually the voltage of the word line. When the voltage of the word line is increased gradually by the driver, the sense amplifier senses the first and second threshold voltages in ascending order.

公开(公告)号：US09224488B2

公开(公告)日：2015-12-29

申请号：US13830263

申请日：2013-03-14

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Go Shikata ,  Takuya Futatsuyama

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3418

摘要： According to one embodiment, a semiconductor memory device includes the following structure. A memory cell array includes memory cells arranged at positions where bit lines and word lines cross are arranged on a semiconductor substrate. A sense amplifier reads data stored in the memory cell. The hookup region includes a transfer transistor arranged between the memory cell array and the sense amplifier. One end of a current path of the transfer transistor is connected to a first interconnect formed between the semiconductor substrate and the bit line. The other end of the current path is connected to the sense amplifier. A guard ring region is arranged between the memory cell array and the hookup region. A contact plug is arranged to overlap the guard ring region.

摘要翻译： 根据一个实施例，半导体存储器件包括以下结构。 存储单元阵列包括布置在位线和字线交叉的位置处的存储单元布置在半导体衬底上。 读出放大器读取存储在存储单元中的数据。 连接区域包括布置在存储单元阵列和读出放大器之间的转移晶体管。 传输晶体管的电流路径的一端连接到形成在半导体衬底和位线之间的第一互连。 电流路径的另一端连接到读出放大器。 保护环区域布置在存储单元阵列和连接区域之间。 接触塞被布置成与保护环区域重叠。

公开(公告)号：US20140071763A1

公开(公告)日：2014-03-13

申请号：US13830263

申请日：2013-03-14

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Go Shikata ,  Takuya Futatsuyama

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3418

摘要： According to one embodiment, a semiconductor memory device includes the following structure. A memory cell array includes memory cells arranged at positions where bit lines and word lines cross are arranged on a semiconductor substrate. A sense amplifier reads data stored in the memory cell. The hookup region includes a transfer transistor arranged between the memory cell array and the sense amplifier. One end of a current path of the transfer transistor is connected to a first interconnect formed between the semiconductor substrate and the bit line. The other end of the current path is connected to the sense amplifier. A guard ring region is arranged between the memory cell array and the hookup region. A contact plug is arranged to overlap the guard ring region.

摘要翻译： 根据一个实施例，半导体存储器件包括以下结构。 存储单元阵列包括布置在位线和字线交叉的位置处的存储单元布置在半导体衬底上。 读出放大器读取存储在存储单元中的数据。 连接区域包括布置在存储单元阵列和读出放大器之间的转移晶体管。 传输晶体管的电流路径的一端连接到形成在半导体衬底和位线之间的第一互连。 电流路径的另一端连接到读出放大器。 保护环区域布置在存储单元阵列和连接区域之间。 接触塞被布置成与保护环区域重叠。