POWER EFFICIENT AND SCALABLE CO-PACKAGED OPTICAL DEVICES

    公开(公告)号:US20220103261A1

    公开(公告)日:2022-03-31

    申请号:US17478095

    申请日:2021-09-17

    Abstract: A co-packaged optical-electrical chip can include an application-specific integrated circuit (ASIC) and a plurality of optical modules, such as optical transceivers. The ASIC and each of the optical modules can exchange electrical signaling via integrated electrical paths. The ASIC can include Ethernet switch, error correction, bit-to-symbol mapping/demapping, and digital signal processing circuits to pre-compensate and post-compensate channel impairments (e.g., inter-channel/intra-channel impairments) in electrical and optical domains. The co-packaged inter-chip interface can be scaled to handle different data rates using spectral efficient signaling formats (e.g., QAM-64, PAM-8) without adding additional data lines to a given design and without significantly increasing the power consumption of the design.

    Signal characteristic information for networks

    公开(公告)号:US10182002B1

    公开(公告)日:2019-01-15

    申请号:US15693066

    申请日:2017-08-31

    Abstract: A device may cause an optical signal to be transmitted via a network path. The device may receive, from a network device, a link layer discover protocol (LLDP) message. The LLDP message may include signal characteristic information regarding the optical signal. The device may adjust transmission of the optical signal based on receiving the LLDP message. The device may cause an adjusted optical signal to be transmitted via the network path based on adjusting transmission of the optical signal.

    POWER EFFICIENT AND SCALABLE CO-PACKAGED OPTICAL DEVICES

    公开(公告)号:US20230291478A1

    公开(公告)日:2023-09-14

    申请号:US18197266

    申请日:2023-05-15

    CPC classification number: H04B10/40 H04L1/0041 H04L1/0045 H04L27/34

    Abstract: A co-packaged optical-electrical chip can include an application-specific integrated circuit (ASIC) and a plurality of optical modules, such as optical transceivers. The ASIC and each of the optical modules can exchange electrical signaling via integrated electrical paths. The ASIC can include Ethernet switch, error correction, bit-to-symbol mapping/demapping, and digital signal processing circuits to pre-compensate and post-compensate channel impairments (e.g., inter-channel/intra-channel impairments) in electrical and optical domains. The co-packaged inter-chip interface can be scaled to handle different data rates using spectral efficient signaling formats (e.g., QAM-64, PAM-8) without adding additional data lines to a given design and without significantly increasing the power consumption of the design.

    Power efficient and scalable co-packaged optical devices

    公开(公告)号:US11159240B1

    公开(公告)日:2021-10-26

    申请号:US17038453

    申请日:2020-09-30

    Abstract: A co-packaged optical-electrical chip can include an application-specific integrated circuit (ASIC) and a plurality of optical modules, such as optical transceivers. The ASIC and each of the optical modules can exchange electrical signaling via integrated electrical paths. The ASIC can include Ethernet switch, error correction, bit-to-symbol mapping/demapping, and digital signal processing circuits to pre-compensate and post-compensate channel impairments (e.g., inter-channel/intra-channel impairments) in electrical and optical domains. The co-packaged inter-chip interface can be scaled to handle different data rates using spectral efficient signaling formats (e.g., QAM-64, PAM-8) without adding additional data lines to a given design and without significantly increasing the power consumption of the design.

    Detecting a transceiver using a noise optical signal

    公开(公告)号:US10547379B2

    公开(公告)日:2020-01-28

    申请号:US15978792

    申请日:2018-05-14

    Abstract: A method may include causing a signal to be transmitted that includes a plurality of wavelengths. The signal may be transmitted via an optical fiber that is associated with a particular wavelength. The particular wavelength may be included in the plurality of wavelengths. The method may include filtering the signal, based on the particular wavelength, to generate a filtered signal. The filtered signal may include the particular wavelength. The method may include detecting the filtered signal in association with the optical fiber. The method may include determining the particular wavelength based on the filtered signal. The method may include storing or providing information identifying at least one of the particular wavelength, the optical fiber, or a transmitter that transmitted the signal.

    Detecting a transceiver using a noise optical signal

    公开(公告)号:US09973836B1

    公开(公告)日:2018-05-15

    申请号:US15067806

    申请日:2016-03-11

    CPC classification number: H04Q11/0071 H04Q2011/0009 H04Q2011/0032

    Abstract: A method may include causing a signal to be transmitted that includes a plurality of wavelengths. The signal may be transmitted via an optical fiber that is associated with a particular wavelength. The particular wavelength may be included in the plurality of wavelengths. The method may include filtering the signal, based on the particular wavelength, to generate a filtered signal. The filtered signal may include the particular wavelength. The method may include detecting the filtered signal in association with the optical fiber. The method may include determining the particular wavelength based on the filtered signal. The method may include storing or providing information identifying at least one of the particular wavelength, the optical fiber, or a transmitter that transmitted the signal.

    Power efficient and scalable co-packaged optical devices

    公开(公告)号:US11689289B2

    公开(公告)日:2023-06-27

    申请号:US17478095

    申请日:2021-09-17

    CPC classification number: H04B10/40 H04L1/0041 H04L1/0045 H04L27/34

    Abstract: A co-packaged optical-electrical chip can include an application-specific integrated circuit (ASIC) and a plurality of optical modules, such as optical transceivers. The ASIC and each of the optical modules can exchange electrical signaling via integrated electrical paths. The ASIC can include Ethernet switch, error correction, bit-to-symbol mapping/demapping, and digital signal processing circuits to pre-compensate and post-compensate channel impairments (e.g., inter-channel/intra-channel impairments) in electrical and optical domains. The co-packaged inter-chip interface can be scaled to handle different data rates using spectral efficient signaling formats (e.g., QAM-64, PAM-8) without adding additional data lines to a given design and without significantly increasing the power consumption of the design.

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