公开(公告)号：US09319347B1

公开(公告)日：2016-04-19

申请号：US14814820

申请日：2015-07-31

Applicant: Juniper Networks, Inc.

Inventor： Pradeep Sindhu ,  Jean-Marc Frailong ,  Sarin Thomas ,  Srihari Raju Vegesna ,  David James Ofelt ,  Chang-Hong Wu

IPC: H04L12/28 ,  H04L12/931 ,  H04L12/761 ,  H04L12/18 ,  H04L12/861 ,  H04L29/08

CPC classification number: H04L45/16 ,  H04L12/1863 ,  H04L49/201 ,  H04L49/90 ,  H04L67/1095

Abstract: In general, the invention is directed to techniques for reducing deadlocks that may arise when performing fabric replication. For example, as described herein, a network device includes packet replicators that each comprises a plurality of resource partitions. A replication data structure for a packet received by the network device includes packet replicator nodes that are arranged hierarchically to occupy one or more levels of the replication data structure. Each of the resource partitions in each of the plurality of packet replicators is associated with a different level of the replication data structure. The packet replicators replicate the packet according to the replication data structure, and each of the packet replicators handles the packet using the one of the resource partitions of the packet replicator that is associated with the level of the replication data structure occupied by the node that corresponds to that particular packet replicator.

公开(公告)号：US10069596B1

公开(公告)日：2018-09-04

申请号：US15388901

申请日：2016-12-22

Applicant: Juniper Networks, Inc.

Inventor： David P. Chengson ,  Granthana Kattehalli Rangaswamy ,  David James Ofelt ,  Edward C. Priest ,  Bhavesh Patel

IPC: H04L1/00 ,  H04L1/24 ,  H04L27/06

Abstract: In an example of this disclosure, a method may include receiving, by a bit error location analyzer, a split information signal at a second data rate derived from an information signal at a first data rate. In this example, the second data rate is less than the first data rate, and the bit error location analyzer may be incapable of performing error analysis at the first data rate The method may include performing error analysis, by the bit error location analyzer, on information represented by the split information signal. In some examples, performing error analysis may include comparing the information represented by the split information signal to an information seed to determine a plurality of bit error locations in the information represented by the split information signal relative to the information seed.

公开(公告)号：US09838138B1

公开(公告)日：2017-12-05

申请号：US14984837

申请日：2015-12-30

Applicant: Juniper Networks, Inc.

Inventor： Murat Arabaci ,  Marianna Pepe ,  Massimiliano Salsi ,  Philip A. Thomas ,  David James Ofelt

IPC: H04B10/588

CPC classification number: H04B10/588 ,  H04B10/612 ,  H04B10/613 ,  H04B10/614

Abstract: Techniques are described for determining pre-compensation parameters to compensate for signal integrity degradation along a signal path. A processor generates a first digital signal and receives a second digital signal. The second digital signal is generated from an optical-to-electrical conversion of a feedback optical signal that is generated from an electrical-to-optical conversion of an electrical signal by an optical module. The processor determines the pre-compensation parameters based on the first and second digital signals.