Fan-out in ball grid array (BGA) package

    公开(公告)号:US10249596B1

    公开(公告)日:2019-04-02

    申请号:US15198253

    申请日:2016-06-30

    Abstract: In some examples, a device includes at least two integrated circuits (ICs) and a first multi-chip module (MCM) substrate coupled to the at least two ICs, the first MCM substrate comprising a first ball grid array (BGA), wherein the first BGA comprises a first pitch indicative of a distance between balls of the first BGA. The device further includes a second MCM substrate coupled to the first MCM substrate with the first BGA, the second MCM substrate comprising a second BGA, wherein the second BGA comprises a second pitch indicative of a distance between balls of the second BGA, and wherein the second pitch is greater than the first pitch. The device further includes a printed circuit board (PCB) coupled to the second MCM substrate with the second BGA, wherein the first MCM substrate and the second MCM substrate comprise organic, non-silicon insulating material.

    Supplemental connection fabric for chassis-based network device

    公开(公告)号:US10277534B2

    公开(公告)日:2019-04-30

    申请号:US15170608

    申请日:2016-06-01

    Abstract: A system may receive, by a switching component of the system, network traffic to be provided to an I/O component of the network device. The system may route, by the switching component, the network traffic to the I/O component based on whether the I/O component is connected to the switching component via the first connections and/or via second connections. The first connections may be connections via a chassis of the system. The second connections may be connections via a connector component that is removable from the switching component. The network traffic may be routed via the first connections and the second connections when the I/O component is connected via the first connections and the second connections. The network traffic may be routed via the first connections and not via the second connections when the I/O component is connected via the first connections and not via the second connections.

    Systems and methods for error detection and correction

    公开(公告)号:US10069596B1

    公开(公告)日:2018-09-04

    申请号:US15388901

    申请日:2016-12-22

    Abstract: In an example of this disclosure, a method may include receiving, by a bit error location analyzer, a split information signal at a second data rate derived from an information signal at a first data rate. In this example, the second data rate is less than the first data rate, and the bit error location analyzer may be incapable of performing error analysis at the first data rate The method may include performing error analysis, by the bit error location analyzer, on information represented by the split information signal. In some examples, performing error analysis may include comparing the information represented by the split information signal to an information seed to determine a plurality of bit error locations in the information represented by the split information signal relative to the information seed.

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