公开(公告)号：US06518797B2

公开(公告)日：2003-02-11

申请号：US09753268

申请日：2000-12-29

Applicant: Jungwook Yang

Inventor： Jungwook Yang

IPC: H03K19086

CPC classification number: H03K19/01837 ,  H03K19/0826 ,  H03K19/086

Abstract: In a current mode logic (CML) circuit, a high impedance state is implemented at the output for a bi-directional buffer. The output common mode voltage can be adjusted at the same time, which is particularly useful for a CML off-chip driver.

Abstract translation: 在电流模式逻辑（CML）电路中，在双向缓冲器的输出端实现高阻抗状态。 可以同时调节输出共模电压，这对于CML片外驱动器特别有用。

公开(公告)号：US06344877B1

公开(公告)日：2002-02-05

申请号：US08873539

申请日：1997-06-12

Applicant: Sudhir Muniswamy Gowda ,  Hyun Jong Shin ,  Hon-Sum Philip Wong ,  Peter Hong Xiao ,  Jungwook Yang

Inventor： Sudhir Muniswamy Gowda ,  Hyun Jong Shin ,  Hon-Sum Philip Wong ,  Peter Hong Xiao ,  Jungwook Yang

IPC: H04N964

CPC classification number: H04N5/3745 ,  H04N5/3575 ,  H04N5/361 ,  H04N5/3651

Abstract: Disclosed is an image sensor including one or more dummy pixels that produce a reference signal which is used to compensate for errors within the devices of the main pixel cells. In one embodiment, at least one dummy pixel is used in conjunction with other circuitry to correct for nonlinearities in the transfer characteristic of a source follower transistor within each pixel. In another embodiment, an array of dummy pixels is used to correct for leakage current within the pixels during an electronic shutter mode of operation. The two techniques can be combined whereby both threshold voltage mismatch and leakage current are compensated for.

Abstract translation: 公开了一种图像传感器，其包括产生用于补偿主像素单元的装置内的误差的参考信号的一个或多个虚拟像素。 在一个实施例中，至少一个虚拟像素与其他电路结合使用，以校正每个像素内的源极跟随器晶体管的传输特性中的非线性。 在另一个实施例中，在电子快门操作模式期间，使用虚拟像素阵列来校正像素内的漏电流。 可以组合两种技术，由此补偿阈值电压失配和泄漏电流。

公开(公告)号：US5877715A

公开(公告)日：1999-03-02

申请号：US873537

申请日：1997-06-12

Applicant: Sudhir Muniswamy Gowda ,  Hyun Jong Shin ,  Hon-Sum Philip Wong ,  Peter Hong Xiao ,  Jungwook Yang

Inventor： Sudhir Muniswamy Gowda ,  Hyun Jong Shin ,  Hon-Sum Philip Wong ,  Peter Hong Xiao ,  Jungwook Yang

IPC: H03M1/12 ,  H03M1/56 ,  H04N5/363 ,  H04N5/374 ,  H04N5/378 ,  H04N1/40 ,  H03M1/46

CPC classification number: H03M1/1295 ,  H03M1/1023 ,  H03M1/123 ,  H04N3/155 ,  H03M1/56

Abstract: Disclosed is a circuit for performing correlated double sampling entirely in the digital domain. In an exemplary embodiment, the circuit includes a plurality of comparators, each having a first input coupled to an associated data line for receiving first and second signals in first and second sampling intervals, respectively. A time varying reference signal is applied to the second input of each comparator. A plurality of up/down counters are coupled to respective ones of the comparators, and each is operable to count in a first direction during the first sampling interval and in an opposite direction during the second sampling interval. Each up/down counter is caused to stop counting when the amplitude of the variable reference signal substantially equals the amplitude of the respective first or second signal. As a result, each up/down counter provides an output representing a subtraction of one of said first or second signals from the other. The invention has particular utility when used in conjunction with a CMOS image sensor.

Abstract translation: 公开了一种完全在数字领域进行相关双重采样的电路。 在示例性实施例中，电路包括多个比较器，每个比较器具有耦合到相关联的数据线的第一输入，用于分别在第一和第二采样间隔中接收第一和第二信号。 时变参考信号被施加到每个比较器的第二输入端。 多个向上/向下计数器耦合到相应的比较器，并且每个可操作以在第一采样间隔期间以第一方向计数，并且在第二采样间隔期间以相反的方向计数。 当可变参考信号的幅度基本上等于相应的第一或第二信号的幅度时，使每个向上/向下计数器停止计数。 结果，每个向上/向下计数器提供表示从另一个减去所述第一或第二信号之一的输出。 当与CMOS图像传感器结合使用时，本发明具有特别的用途。

公开(公告)号：US08796036B2

公开(公告)日：2014-08-05

申请号：US13173851

申请日：2011-06-30

Applicant: Keith Fife ,  Jungwook Yang

Inventor： Keith Fife ,  Jungwook Yang

IPC: G01N15/06 ,  G01N27/414

CPC classification number: G01N27/4148 ,  H03K5/003 ,  Y10S436/806 ,  Y10S436/807 ,  Y10T436/11

Abstract: An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples.

公开(公告)号：US08487790B2

公开(公告)日：2013-07-16

申请号：US13174562

申请日：2011-06-30

Applicant: Keith Fife ,  Jungwook Yang

Inventor： Keith Fife ,  Jungwook Yang

IPC: H03M9/00

CPC classification number: G01N27/4148 ,  C12Q1/6869 ,  G01J1/46 ,  G01N27/4143 ,  G01N27/4145 ,  G01N33/00 ,  G01R29/26 ,  H01L27/14609 ,  H01L27/14632 ,  H01L27/14643 ,  H01L29/66 ,  H01L2924/0002 ,  H04N5/374 ,  Y10T436/25875 ,  H01L2924/00

Abstract: The described embodiments may provide a chemical detection circuit. The chemical detection circuit may comprise a pixel array, a pair of analog-to-digital converter (ADC) circuit blocks, a pair of input/output (I/O) circuit blocks coupled to the pair of ADC circuit blocks respectively, and a plurality of serial link terminals coupled to the pair of IO circuit blocks. The pixel array may comprise a plurality of chemically-sensitive pixels formed in columns and rows. Each chemically-sensitive pixel may comprise: a chemically-sensitive transistor, and a row selection device.

Abstract translation: 所描述的实施例可以提供化学检测电路。 化学检测电路可以包括像素阵列，一对模数转换器（ADC）电路块，分别耦合到该对ADC电路块的一对输入/输出（I / O）电路块，以及一 耦合到所述一对IO电路块的多个串行链路终端。 像素阵列可以包括以列和行形成的多个化学敏感像素。 每个化学敏感像素可以包括：化学敏感晶体管和行选择器件。

公开(公告)号：US07489354B2

公开(公告)日：2009-02-10

申请号：US10752112

申请日：2004-01-06

Applicant: Hae-Seung Lee ,  Keith Glen Fife ,  Lane G. Brooks ,  Jungwook Yang

Inventor： Hae-Seung Lee ,  Keith Glen Fife ,  Lane G. Brooks ,  Jungwook Yang

IPC: H04N5/335

CPC classification number: H04N5/3597 ,  H04N5/363 ,  H04N5/3698 ,  H04N5/374 ,  H04N5/3745

Abstract: A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

公开(公告)号：US06985169B1

公开(公告)日：2006-01-10

申请号：US09021176

申请日：1998-02-09

Applicant: Zhong John Deng ,  Sudhir Muniswamy Gowda ,  John P. Karidis ,  Dale Jonathan Pearson ,  Rama Nand Singh ,  Hon-Sum Philip Wong ,  Jungwook Yang

Inventor： Zhong John Deng ,  Sudhir Muniswamy Gowda ,  John P. Karidis ,  Dale Jonathan Pearson ,  Rama Nand Singh ,  Hon-Sum Philip Wong ,  Jungwook Yang

IPC: H04N7/18 ,  H04N7/14

CPC classification number: H04N1/00307 ,  H04N1/00315 ,  H04N1/00347 ,  H04N1/19594 ,  H04N2201/0084 ,  H04N2201/0086

Abstract: An image capture system for mobile communications systems includes an imaging device for capturing optical image data and a data transfer apparatus coupled to a communications device communications device for transferring the optical image data to the communications device for transmittal over a communications network.

Abstract translation: 用于移动通信系统的图像捕获系统包括用于捕获光学图像数据的成像设备和耦合到通信设备通信设备的数据传送设备，用于将光学图像数据传送到通信设备以通过通信网络传输。

公开(公告)号：US06630864B2

公开(公告)日：2003-10-07

申请号：US10341020

申请日：2003-01-13

Applicant: Jungwook Yang

Inventor： Jungwook Yang

IPC: H03F345

CPC classification number: H03F3/45089 ,  H03F3/45098 ,  H03F3/45502 ,  H03F2203/45646 ,  H03F2203/45702

Abstract: A system and method of controlling the operation of linear variable-gain amplifiers to allow for such linear variable gain amplifiers to have a wider operating range at high current levels, control inputs for selectable gains and improved low-voltage operation. In a first mode, the amplifier includes an additional source of current to allow for an enhanced operating range. In a second embodiment, the amplifier includes a plurality of selective resistive levels and a selection system which allows the selection of one of the resistive levels which, in turn, controls the gain range of the amplifier system of the present invention. A third embodiment of the present invention illustrates the use of an amplifier system useful for a low voltage input signal to reduce errors caused by variations in the base to emitter in the two transistors providing the amplification. Also disclosed are embodiments for reducing the error in the amplifier output by providing additional stages to provide error reducing components which are added to the amplifier output.

公开(公告)号：US06563382B1

公开(公告)日：2003-05-13

申请号：US09685813

申请日：2000-10-10

Applicant: Jungwook Yang

Inventor： Jungwook Yang

IPC: H03F345

CPC classification number: H03F3/45089 ,  H03F3/45098 ,  H03F3/45502 ,  H03F2203/45646 ,  H03F2203/45702

Abstract: A system and method of controlling the operation of linear variable-gain amplifiers to allow for such linear variable gain amplifiers to have a wider operating range at high current levels, control inputs for selectable gains and improved low-voltage operation. In a first mode, the amplifier includes an additional source of current to allow for an enhanced operating range. In a second embodiment, the amplifier includes a plurality of selective resistive levels and a selection system which allows the selection of one of the resistive levels which, in turn, controls the gain range of the amplifier system of the present invention. A third embodiment of the present invention illustrates the use of an amplifier system useful for a low voltage input signal to reduce errors caused by variations in the base to emitter in the two transistors providing the amplification. Also disclosed are embodiments for reducing the error in the amplifier output by providing additional stages to provide error reducing components which are added to the amplifier output.

Abstract translation: 控制线性可变增益放大器的操作的系统和方法，以允许这种线性可变增益放大器在高电流水平下具有更宽的工作范围，控制输入以获得可选择的增益和改进的低电压操作。 在第一模式中，放大器包括额外的电流源以允许增强的操作范围。 在第二实施例中，放大器包括多个选择性电阻电平和选择系统，其允许选择电阻电平中的一个，这进而控制本发明的放大器系统的增益范围。 本发明的第三实施例示出了对于低电压输入信号有用的放大器系统的用途，以减少由提供放大的两个晶体管中的基极到发射极的变化引起的误差。 还公开了用于通过提供附加级来提供放大器输出中的误差减小部件来减小放大器输出中的误差的实施例。

公开(公告)号：US06429691B1

公开(公告)日：2002-08-06

申请号：US09751508

申请日：2000-12-29

Applicant: Jungwook Yang

Inventor： Jungwook Yang

IPC: H03K1920

CPC classification number: H03K19/017527

Abstract: A circuit provides differential logic signals and includes a differential-input circuit having a first differential input and a second differential input. A first unit receives an input voltage signal and a supply voltage for providing a first voltage to the first differential input via a first node. A second unit receives the supply voltage for providing a second voltage to the second differential input via a second node. The differential-input circuit outputs a signal in accordance with the first and second voltages.

Abstract translation: 电路提供差分逻辑信号，并且包括具有第一差分输入和第二差分输入的差分输入电路。 第一单元接收输入电压信号和用于经由第一节点向第一差分输入提供第一电压的电源电压。 第二单元接收用于经由第二节点向第二差分输入提供第二电压的电源电压。 差分输入电路根据第一和第二电压输出信号。