公开(公告)号：US08330218B2

公开(公告)日：2012-12-11

申请号：US12870913

申请日：2010-08-30

申请人： Jong-ho Park ,  Hyi-Jeong Park ,  Hye-mi Kim ,  Chang-Ki Jeon

发明人： Jong-ho Park ,  Hyi-Jeong Park ,  Hye-mi Kim ,  Chang-Ki Jeon

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/8249 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7809 ,  H01L29/7812

摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 使用DMOS器件的半导体器件包括：形成第一导电型阱的半导体衬底; 形成在所述半导体衬底上的第一导电型栅极电极，所述栅极绝缘层介于所述栅电极和所述半导体衬底之间; 形成在所述半导体基板上并与所述栅电极分离的第二导电型体电极; 形成在所述半导体基板上并与所述栅电极和所述主体电极分离的第一导电型漏电极; 形成在所述体电极下方的所述阱内的第二导电型第一体区域; 第二导电类型的第二主体区域，其从所述第一主体区域延伸到所述栅极绝缘层并形成在所述阱中; 形成在所述第二主体区域中并从所述第一主体区域延伸到所述栅极绝缘层的第一导电型源极区域; 以及第一导电型源电极，其从所述源极区域延伸，以在所述半导体衬底上围绕所述栅极电极，所述绝缘层介于所述源电极和栅电极之间。

公开(公告)号：US20090250753A1

公开(公告)日：2009-10-08

申请号：US12414172

申请日：2009-03-30

申请人： Jong-ho Park ,  Chang-Ki Jeon ,  Hyi-Jeong Park ,  Hye-mi Kim

发明人： Jong-ho Park ,  Chang-Ki Jeon ,  Hyi-Jeong Park ,  Hye-mi Kim

IPC分类号： H01L29/78 ,  H01L27/06 ,  H01L21/336 ,  H01L21/8249

CPC分类号： H01L21/8249 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7809 ,  H01L29/7812

摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 使用DMOS器件的半导体器件包括：形成第一导电型阱的半导体衬底; 形成在所述半导体衬底上的第一导电型栅极电极，所述栅极绝缘层介于所述栅电极和所述半导体衬底之间; 形成在所述半导体基板上并与所述栅电极分离的第二导电型体电极; 形成在所述半导体基板上并与所述栅电极和所述主体电极分离的第一导电型漏电极; 形成在所述体电极下方的所述阱内的第二导电型第一体区域; 第二导电类型的第二主体区域，其从所述第一主体区域延伸到所述栅极绝缘层并形成在所述阱中; 形成在所述第二主体区域中并从所述第一主体区域延伸到所述栅极绝缘层的第一导电型源极区域; 以及第一导电型源电极，其从所述源极区域延伸，以在所述半导体衬底上围绕所述栅极电极，所述绝缘层介于所述源电极和栅电极之间。

公开(公告)号：US07803676B2

公开(公告)日：2010-09-28

申请号：US12414172

申请日：2009-03-30

申请人： Jong-ho Park ,  Chang-Ki Jeon ,  Hyi-Jeong Park ,  Hye-mi Kim

发明人： Jong-ho Park ,  Chang-Ki Jeon ,  Hyi-Jeong Park ,  Hye-mi Kim

IPC分类号： H01L21/8238 ,  H01L21/331 ,  H01L21/8222

CPC分类号： H01L21/8249 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7809 ,  H01L29/7812

摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 使用DMOS器件的半导体器件包括：形成第一导电型阱的半导体衬底; 形成在所述半导体衬底上的第一导电型栅极电极，所述栅极绝缘层介于所述栅电极和所述半导体衬底之间; 形成在所述半导体基板上并与所述栅电极分离的第二导电型体电极; 形成在所述半导体基板上并与所述栅电极和所述主体电极分离的第一导电型漏电极; 形成在所述体电极下方的所述阱内的第二导电型第一体区域; 第二导电类型的第二主体区域，其从所述第一主体区域延伸到所述栅极绝缘层并形成在所述阱中; 形成在所述第二主体区域中并从所述第一主体区域延伸到所述栅极绝缘层的第一导电型源极区域; 以及第一导电型源电极，其从所述源极区域延伸，以在所述半导体衬底上围绕所述栅极电极，所述绝缘层介于所述源电极和栅电极之间。

公开(公告)号：US5913114A

公开(公告)日：1999-06-15

申请号：US7534

申请日：1998-01-15

申请人： Sun-Hak Lee ,  Chang-Ki Jeon ,  Cheol-Joong Kim

发明人： Sun-Hak Lee ,  Chang-Ki Jeon ,  Cheol-Joong Kim

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H01L21/8238

CPC分类号： H01L29/66712 ,  H01L21/8249 ,  H01L29/7809 ,  H01L29/42368

摘要： A semiconductor device, and a method of manufacturing the same, containing a high voltage DMOS transistor, a low voltage CMOS transistor, and a bipolar transistor in a single substrate. The steps include forming an isolation layer within the substrate in an isolation region between each of a DMOS region, a CMOS region, or a bipolar region. A first oxide layer of variable thickness is formed on the substrate, a thick second oxide layer is formed on the isolation layer, and a polysilicon layer is formed on both oxide layers. The polysilicon layer is patterned to form gate patterns on the first oxide layer and resistive patterns on the second oxide layer. The gate pattern is then doped but the resistive pattern is undoped. The thickness of the first oxide layer in the DMOS region is greater than the thickness of the first oxide layer in the CMOS region.

摘要翻译： 在单个基板中包含高电压DMOS晶体管，低电压CMOS晶体管和双极晶体管的半导体器件及其制造方法。 这些步骤包括在DMOS区域，CMOS区域或双极区域中的每一个之间的隔离区域内在衬底内形成隔离层。 在衬底上形成可变厚度的第一氧化物层，在隔离层上形成厚的第二氧化物层，并且在两个氧化物层上形成多晶硅层。 图案化多晶硅层以在第一氧化物层上形成栅极图案，并在第二氧化物层上形成电阻图案。 然后掺杂栅极图案，但是电阻图案是未掺杂的。 DMOS区域中的第一氧化物层的厚度大于CMOS区域中第一氧化物层的厚度。

公开(公告)号：US20090020814A1

公开(公告)日：2009-01-22

申请号：US12013354

申请日：2008-01-11

申请人： Yong-Cheol Choi ,  Chang-Ki Jeon ,  Sang-Hyun Lee

发明人： Yong-Cheol Choi ,  Chang-Ki Jeon ,  Sang-Hyun Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/7835

摘要： A high voltage semiconductor device includes a source region of a first conductivity type having an elongated projection with two sides and a rounded tip in a semiconductor substrate. A drain region of the first conductivity type is laterally spaced from the source region in the semiconductor substrate. A gate electrode extends along the projection of the source region on the semiconductor substrate between the source and drain regions. Top floating regions of a second conductivity type are disposed between the source and drain regions in the shape of arched stripes extending along the rounded tip of the projection of the source region. The top floating regions are laterally spaced from one another by regions of the first conductivity type to thereby form alternating P-N regions along the lateral dimension.

摘要翻译： 高电压半导体器件包括第一导电类型的源极区域，其具有两侧的细长突起和半导体衬底中的圆形尖端。 第一导电类型的漏极区域与半导体衬底中的源极区域横向间隔开。 栅电极沿着半导体衬底上的源极区域的源极和漏极区域的突出部分延伸。 第二导电类型的顶部浮动区域设置在沿着源极区域的投影的圆形尖端延伸的弓形条形状的源极和漏极区域之间。 顶部浮动区域通过第一导电类型的区域彼此横向间隔开，从而沿横向尺寸形成交替的P-N区域。

公开(公告)号：US5918114A

公开(公告)日：1999-06-29

申请号：US855459

申请日：1997-05-13

申请人： Yong-Cheol Choi ,  Chang-Ki Jeon

发明人： Yong-Cheol Choi ,  Chang-Ki Jeon

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L29/78 ,  H01L21/332

CPC分类号： H01L29/7813

摘要： Methods of forming vertical trench-gate semiconductor devices include the steps of patterning an oxidation resistant layer having an opening therein, on a face of a semiconductor substrate, and then forming a trench in the semiconductor substrate, opposite the opening in the oxidation resistant layer. An insulated gate electrode is then formed in the trench. The face of the semiconductor substrate is then oxidized to define self-aligned electrically insulating regions in the opening and at a periphery of the patterned oxidation resistant layer. Here, the patterned oxidation resistant layer is used as an oxidation mask so that portions of the substrate underlying the oxidation resistant layer are not substantially oxidized. Source and body region dopants of first and second conductivity type, respectively, are then implanted into the substrate to define preliminary source and body regions which extend adjacent a sidewall of the trench. During the implanting step, the electrically insulating regions are used as a self-aligned implant mask. The implanted dopants are then diffused into the substrate to define source and body regions adjacent upper and intermediate portions of the sidewall of the trench, respectively.

摘要翻译： 形成垂直沟槽栅极半导体器件的方法包括在半导体衬底的表面上形成其中具有开口的抗氧化层的步骤，然后在半导体衬底中形成与抗氧化层中的开口相反的沟槽。 然后在沟槽中形成绝缘栅电极。 然后氧化半导体衬底的表面以在图案化抗氧化层的开口和周边限定自对准的电绝缘区域。 这里，图案化抗氧化层用作氧化掩模，使得在抗氧化层下面的基底的部分基本上不被氧化。 然后分别将第一和第二导电类型的源区和体区掺杂剂注入到衬底中以限定在沟槽的侧壁附近延伸的初始源极和体区。 在植入步骤期间，电绝缘区域用作自对准植入掩模。 然后将注入的掺杂剂扩散到衬底中以分别限定与沟槽的侧壁的上部和中间部分相邻的源极和体区。

公开(公告)号：US07655979B2

公开(公告)日：2010-02-02

申请号：US11950959

申请日：2007-12-05

申请人： Chang-Ki Jeon ,  Sung-Iyong Kim ,  Tae-hun Kwon

发明人： Chang-Ki Jeon ,  Sung-Iyong Kim ,  Tae-hun Kwon

IPC分类号： H01L29/772 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7823

摘要： There is provided a high voltage gate driver integrated circuit. The high voltage gate driver integrated circuit includes: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and/or a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region.

摘要翻译： 提供了高压栅极驱动器集成电路。 高压栅极驱动器集成电路包括：高电压区域; 围绕高电压区域的接合端接区域; 围绕所述连接端接区域的低电压区域; 设置在所述高电压区域和所述低电压区域之间的电平移位晶体管，所述电平移位晶体管的至少一些部分与所述连接终止区域重叠; 和/或设置在高电压区域和低电压区域之间的高压结电容器，高压结电容器的至少一些部分与接合端接区域重叠。

公开(公告)号：US06489652B1

公开(公告)日：2002-12-03

申请号：US08742754

申请日：1996-11-01

申请人： Chang-Ki Jeon ,  Young-Soo Jang

发明人： Chang-Ki Jeon ,  Young-Soo Jang

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/42368

摘要： A trench DMOS device having improved breakdown characteristics. The trench DMOS device has a gate oxide layer which has a substantially flattened thick portion in the bottom of the trench and which is relatively thinner on the sidewalls. In greater detail, the trench DMOS device comprises a trench formed in a semiconductor substrate, said trench having sidewalls and a bottom, a gate polysilicon layer filled into said trench, and a gate oxide layer formed between said gate polysilicon layer and the sidewalls and bottom of said trench, wherein a bottom part of said gate oxide layer has a thickness greater than both sidewall parts thereof, and a central region of said bottom part is substantially flattened with a thickness greater than boundary regions thereof. Also disclosed is a novel method of fabricating a trench DMOS device.

摘要翻译： 具有改进的击穿特性的沟槽DMOS器件。 沟槽DMOS器件具有栅极氧化物层，其在沟槽的底部具有基本平坦的厚部分，并且在侧壁上相对较薄。 更详细地，沟槽DMOS器件包括形成在半导体衬底中的沟槽，所述沟槽具有侧壁和底部，填充到所述沟槽中的栅极多晶硅层以及形成在所述栅极多晶硅层与侧壁和底部之间的栅极氧化物层 的所述沟槽，其中所述栅极氧化物层的底部具有大于其两个侧壁部分的厚度，并且所述底部部分的中心区域大致平坦化，其厚度大于其边界区域。 还公开了一种制造沟槽DMOS器件的新颖方法。

公开(公告)号：US6087244A

公开(公告)日：2000-07-11

申请号：US300115

申请日：1999-04-27

申请人： Chang-Ki Jeon

发明人： Chang-Ki Jeon

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/20 ,  H01L21/304 ,  H01L21/76 ,  H01L21/763 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/76264 ,  H01L21/763 ,  H01L21/84 ,  H01L27/1203 ,  H01L21/76275 ,  H01L21/76286 ,  Y10S438/938

摘要： Semiconductor-on-insulator (SOI) devices are fabricated by forming first and second semiconductor layers of opposite conductivity types, at a first face of a substrate. An insulating layer is formed on the first and second semiconductor layers. A trench is formed through the insulating layer extending between the first and second semiconductor layers and extending into the substrate. A portion of the substrate is removed from a second face which is opposite the first face, to define respective first and second active regions on the respective first and second semiconductor layers.

摘要翻译： 绝缘体上半导体（SOI）器件通过在衬底的第一面上形成具有相反导电类型的第一和第二半导体层来制造。 绝缘层形成在第一和第二半导体层上。 通过在第一和第二半导体层之间延伸并延伸到衬底中的绝缘层形成沟槽。 从与第一面相对的第二面去除衬底的一部分，以在相应的第一和第二半导体层上限定相应的第一和第二有源区。

公开(公告)号：US08217487B2

公开(公告)日：2012-07-10

申请号：US12763689

申请日：2010-04-20

申请人： Yongcheol Choi ,  Chang-Ki Jeon ,  Minsuk Kim ,  Donghwan Kim

发明人： Yongcheol Choi ,  Chang-Ki Jeon ,  Minsuk Kim ,  Donghwan Kim

IPC分类号： H02M3/07 ,  H01L21/70

CPC分类号： H03K17/6871 ,  H03K17/063 ,  H03K17/567 ,  H03K2217/0081

摘要： Disclosed is a power semiconductor device including a bootstrap circuit. The power semiconductor device includes a high voltage unit that provides a high voltage control signal so that a high voltage is output; a low voltage unit that provides a low voltage control signal so that a ground voltage is output, and is spaced apart from the high voltage unit; a charge enable unit that is electrically connected to the low voltage unit and charges a bootstrap capacitor for supplying power to the high voltage unit when the high voltage is output, when the ground voltage is output; and a high voltage cut-off unit that cuts off the high voltage when the high voltage is output so that the high voltage is not applied to the charge enable unit, and includes a first terminal electrically connected to the charge enable unit and a second terminal electrically connected to the high voltage unit.

摘要翻译： 公开了一种包括自举电路的功率半导体器件。 功率半导体器件包括提供高电压控制信号以便输出高电压的高电压单元; 提供低电压控制信号以便输出接地电压并与高电压单元间隔开的低压单元; 充电使能单元，当输出所述接地电压时，电连接到所述低电压单元并对输出高电压单元的自举电容充电; 以及高压截止单元，其在输出高电压时切断高电压，使得高电压不被施加到充电使能单元，并且包括电连接到充电使能单元的第一端子和第二端子 电连接到高压单元。