公开(公告)号：US09059196B2

公开(公告)日：2015-06-16

申请号：US14070989

申请日：2013-11-04

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliot ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu ,  Christa R. Willets

IPC: H01L21/762 ,  H01L29/73 ,  H01L29/66 ,  H01L29/732

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.

Abstract translation: 双极结型晶体管的器件结构，设计结构和制造方法。 由包含第一半导体材料的第一层和由第二半导体材料组成的第二层设置在包含双极结型晶体管的第一端子的衬底上。 第二层设置在第一层上，并且在第二层上形成图案化的蚀刻掩模。 沟槽延伸穿过图案硬掩模层，第一层和第二层并进入衬底。 沟槽限定了与第二层的一部分堆叠的第一层的一部分。 使用选择性蚀刻工艺来相对于第一层的截面来缩小第二层的截面以限定第二端子并且加宽衬底中的沟槽的一部分以削弱第一层的部分。

公开(公告)号：US20150123245A1

公开(公告)日：2015-05-07

申请号：US14070989

申请日：2013-11-04

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu ,  Christa R. Willets

IPC: H01L29/66 ,  H01L29/732

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.

公开(公告)号：US20150041956A1

公开(公告)日：2015-02-12

申请号：US14492582

申请日：2014-09-22

Applicant: International Business Machines Corporation

Inventor： Peng Cheng ,  Peter B. Gray ,  Vibhor Jain ,  Robert K. Leidy ,  Qizhi Liu

IPC: H01L29/732

CPC classification number: H01L29/732 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/66242 ,  H01L29/7378

Abstract: Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.

Abstract translation: 双极结型晶体管的器件结构和设计结构。 器件结构包括衬底中的集电极区域，延伸到衬底中并由电绝缘体构成的多个隔离结构以及衬底中的隔离区域。 隔离结构具有长度并且以横向于长度的间距布置，使得每个相邻的一对隔离结构被基板的相应部分分开。 隔离区域通过集电区域的第一部分与隔离结构中的至少一个横向分离。 隔离区域将收集区域的第二部分与收集器区域的第一部分横向分离。 器件结构还包括在集电极区域的第二部分上的本征基极和在本征基极上的发射极。 发射极相对于隔离结构的长度具有横向定向的长度。

公开(公告)号：US20150214344A1

公开(公告)日：2015-07-30

申请号：US14677303

申请日：2015-04-02

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu ,  Christa R. Willets

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.

Abstract translation: 双极结型晶体管的器件结构，设计结构和制造方法。 由包含第一半导体材料的第一层和由第二半导体材料构成的第二层设置在包含双极结型晶体管的第一端子的衬底上。 第二层设置在第一层上，并且在第二层上形成图案化的蚀刻掩模。 沟槽延伸穿过图案硬掩模层，第一层和第二层并进入衬底。 沟槽限定了与第二层的一部分堆叠的第一层的一部分。 使用选择性蚀刻工艺来相对于第一层的截面来缩小第二层的截面以限定第二端子并且加宽衬底中的沟槽的一部分以削弱第一层的部分。

公开(公告)号：US08921195B2

公开(公告)日：2014-12-30

申请号：US13661359

申请日：2012-10-26

Applicant: International Business Machines Corporation

Inventor： Peng Cheng ,  Peter B. Gray ,  Vibhor Jain ,  Robert K. Leidy ,  Qizhi Liu

IPC: H01L29/732

CPC classification number: H01L29/732 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/66242 ,  H01L29/7378

Abstract: Methods for fabricating a device structure, as well as device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.

Abstract translation: 用于制造器件结构的方法，以及用于双极结型晶体管的器件结构和设计结构。 器件结构包括衬底中的集电极区域，延伸到衬底中并由电绝缘体构成的多个隔离结构以及衬底中的隔离区域。 隔离结构具有长度并且以横向于长度的间距布置，使得每个相邻的一对隔离结构被基板的相应部分分开。 隔离区域通过集电区域的第一部分与隔离结构中的至少一个横向分离。 隔离区域将收集区域的第二部分与收集器区域的第一部分横向分离。 器件结构还包括在集电极区域的第二部分上的本征基极和在本征基极上的发射极。 发射极相对于隔离结构的长度具有横向定向的长度。

公开(公告)号：US20140246676A1

公开(公告)日：2014-09-04

申请号：US13782094

申请日：2013-03-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Renata A. Camillo-Castillo ,  Peng Cheng ,  Peter B. Gray ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L29/737 ,  H01L29/66

CPC classification number: H01L29/66242 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/1004 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7378

Abstract: A bipolar device with an entirely monocrystalline intrinsic base to extrinsic base link-up region. To form the device, a first extrinsic base layer, which is amorphous or polycrystalline, is deposited such that it contacts an edge portion of a monocrystalline section of an intrinsic base layer through an opening in a dielectric layer. A second extrinsic base layer is deposited on the first. An anneal is performed, either before or after deposition of the second extrinsic base layer, so that the extrinsic base layers are monocrystalline. An opening is formed through the extrinsic base layers to a dielectric landing pad aligned above a center portion of the monocrystalline section of the intrinsic base layer. The dielectric landing pad is removed and a semiconductor layer is grown epitaxially on exposed monocrystalline surfaces of the extrinsic and intrinsic base layers, thereby forming the entirely monocrystalline intrinsic base to extrinsic base link-up region.

Abstract translation: 具有完全单晶内在基极的外在基极连接区域的双极器件。 为了形成器件，沉积非晶或多晶的第一非本征基层，使得其通过介电层中的开口接触本征基极层的单晶部分的边缘部分。 第二个外在基层沉积在第一个外基层上。 在第二非本征基层沉积之前或之后进行退火，使得外部基极层是单晶的。 通过外部基极层形成开口，形成在本征基极层的单晶部分的中心部分上方的电介质着色垫。 去除电介质着陆焊盘并在外部和本征基极层的暴露的单晶表面上外延生长半导体层，从而形成完全单晶内在碱基到外在碱基连接区。

公开(公告)号：US08710500B2

公开(公告)日：2014-04-29

申请号：US13755192

申请日：2013-01-31

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Erik M. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Qizhi Liu

IPC: H01L29/737

CPC classification number: H01L29/73 ,  H01L21/28518 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.

Abstract translation: 用于制造具有自对准发射极和非本征基极的双极结型晶体管的方法，通过该方法制造的双极结型晶体管以及用于BiCMOS集成电路的设计结构。 使用牺牲发射器基座制造双极结型晶体管，该牺牲发射器基座提供牺牲的心轴，以促进发射极和外部基极之间的自对准。 随后去除牺牲发射器基座以打开延伸到本征基底的发射器窗口。 在发射器窗口中形成发射极，其位于本征基极上。

公开(公告)号：US20130140566A1

公开(公告)日：2013-06-06

申请号：US13755192

申请日：2013-01-31

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Erik M. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Qizhi Liu

IPC: H01L29/73

CPC classification number: H01L29/73 ,  H01L21/28518 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.

Abstract translation: 用于制造具有自对准发射极和非本征基极的双极结型晶体管的方法，通过该方法制造的双极结型晶体管以及用于BiCMOS集成电路的设计结构。 使用牺牲发射器基座制造双极结型晶体管，该牺牲发射器基座提供牺牲的心轴，以促进发射极和外部基极之间的自对准。 随后去除牺牲发射器基座以打开延伸到本征基底的发射器窗口。 在发射器窗口中形成发射极，其位于本征基极上。

公开(公告)号：US20130062668A1

公开(公告)日：2013-03-14

申请号：US13672040

申请日：2012-11-08

Applicant: International Business Machines Corporation

Inventor： Erik M. Dahlstrom ,  Peter B. Gray ,  Qizhi Liu

IPC: H01L29/737 ,  G06F17/50

CPC classification number: H01L29/7378 ,  H01L29/66242

Abstract: Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base.

Abstract translation: 具有降低的基极电阻的异质结双极晶体管，以及用于BiCMOS集成电路的异质结双极晶体管和设计结构的制造方法。 异质结双极晶体管包括在本征基极和外部基极之间的导电层。 导电层由诸如硅化物的导电材料构成，其电阻率低于形成本征碱和非本征基的材料。

公开(公告)号：US20140117493A1

公开(公告)日：2014-05-01

申请号：US13661359

申请日：2012-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Peng Cheng ,  Peter B. Gray ,  Vibhor Jain ,  Robert K. Leidy ,  Qizhi Liu

IPC: H01L29/732 ,  G06F17/50 ,  H01L21/331

CPC classification number: H01L29/732 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/66242 ,  H01L29/7378

Abstract: Methods for fabricating a device structure, as well as device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.

Abstract translation: 用于制造器件结构的方法，以及用于双极结型晶体管的器件结构和设计结构。 器件结构包括衬底中的集电极区域，延伸到衬底中并由电绝缘体构成的多个隔离结构以及衬底中的隔离区域。 隔离结构具有长度并且以横向于长度的间距布置，使得每个相邻的一对隔离结构被基板的相应部分分开。 隔离区域通过集电区域的第一部分与隔离结构中的至少一个横向分离。 隔离区域将收集区域的第二部分与收集器区域的第一部分横向分离。 器件结构还包括在集电极区域的第二部分上的本征基极和在本征基极上的发射极。 发射极相对于隔离结构的长度具有横向定向的长度。