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公开(公告)号：US11462295B2
公开(公告)日：2022-10-04
申请号：US16845259
申请日：2020-04-10
Applicant: International Business Machines Corporation
Inventor： Timothy Meehan , Kirk D. Peterson , John B. DeForge , William V. Huott , Uma Srinivasan , Hyong Uk Kim , Michelle E. Finnefrock , Daniel Rodko
IPC: G11C29/00
Abstract: A system may include an integrated circuit having repair select bits coupled with a central repair register. The repair register may be configured to determine how to broadcast multiple repair actions to a group of repairable circuits. Inclusion of the repair register may function to reduce the total number of latches used to hold repair information.
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公开(公告)号：US09673116B2
公开(公告)日：2017-06-06
申请号：US13733954
申请日：2013-01-04
Applicant: International Business Machines Corporation
Inventor： John B. DeForge , Junjun Li , Alain F. Loiseau , Kirk D. Peterson
CPC classification number: H01L22/34 , G01R31/002 , G01R31/2884
Abstract: An approach for monitoring electrostatic discharge (ESD) event of an integrated circuit. The approach includes a canary device for exhibiting an impedance shift when affected by an ESD pulse, wherein circuit drain of the canary device is connected to an input terminal of the circuit structure. The approach further includes circuit source and logic gates of the canary device, connected to a circuit drain of ESD transistor of the circuit structure, wherein circuit source of the ESD transistor is connected to an output terminal of the circuit structure. The approach further includes a logic gate of the ESD transistor, connected to an enable signal of the circuit structure, and wherein the enable signal is connected to the output terminal through a capacitor of the circuit structure. In addition, the enable signal is also connected to the input terminal through a resistor of the circuit structure.
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公开(公告)号：US10528288B2
公开(公告)日：2020-01-07
申请号：US15847957
申请日：2017-12-20
Applicant: International Business Machines Corporation
Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary , John B. DeForge , Warren E. Maule , Kirk D. Peterson , Sridhar H. Rangarajan , Saravanan Sethuraman
IPC: G06F3/06 , G06F13/16 , G06F11/10 , G11C29/52 , G11C5/02 , G11C11/409 , G11C5/06 , G11C5/04 , G11C7/10 , G11C8/12
Abstract: An aspect includes receiving a request to access one or more memory devices in a stack of memory devices in a memory. Each of the memory devices are communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). A current operating mode of the memory is determined in response to receiving the request. Based at least in part on the current operating mode of the memory being a first mode, a chip select switch is activated to provide access to exactly one of the memory devices in the stack of memory devices. Based at least in part on the current operating mode of the memory being a second mode, the chip select switch is activated to access all of the memory devices in the stack in parallel. The request is serviced using the activated chip select switch.
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公开(公告)号：US20190187930A1
公开(公告)日：2019-06-20
申请号：US15847957
申请日：2017-12-20
Applicant: International Business Machines Corporation
Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary , John B. DeForge , Warren E. Maule , Kirk D. Peterson , Sridhar H. Rangarajan , Saravanan Sethuraman
Abstract: An aspect includes receiving a request to access one or more memory devices in a stack of memory devices in a memory. Each of the memory devices are communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). A current operating mode of the memory is determined in response to receiving the request. Based at least in part on the current operating mode of the memory being a first mode, a chip select switch is activated to provide access to exactly one of the memory devices in the stack of memory devices. Based at least in part on the current operating mode of the memory being a second mode, the chip select switch is activated to access all of the memory devices in the stack in parallel. The request is serviced using the activated chip select switch.
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公开(公告)号：US10109639B1
公开(公告)日：2018-10-23
申请号：US15618695
申请日：2017-06-09
Applicant: International Business Machines Corporation
Inventor： John B. DeForge , John J. Ellis-Monaghan , Terence B. Hook , Kirk D. Peterson
IPC: H01L27/115 , H01L27/1156 , H01L27/11558 , H01L27/12
Abstract: A method fabricates a lateral non-volatile storage cell. The lateral non-volatile storage cell includes a first transistor including a first transistor body formed on a dielectric layer. The first transistor includes a source region and drain region on opposite sides of the first transistor body. A second transistor is laterally adjacent to the first transistor and includes a second transistor body, parallel with the first transistor body, formed on the dielectric layer. A first layer of gate oxide of a first thickness is formed over the first transistor body, and a second layer of gate oxide of a second thickness is formed over a portion of the second transistor body. The first thickness and the second thickness are different. A floating gate is formed over the first layer of gate oxide, the second layer of gate oxide, and the dielectric layer.
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Patent Agency Ranking
公开(公告)号：US10534545B2
公开(公告)日：2020-01-14
申请号：US15847954
申请日：2017-12-20
Applicant: International Business Machines Corporation
Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary , John B. DeForge , Warren E. Maule , Kirk D. Peterson , Sridhar H. Rangarajan , Saravanan Sethuraman
Abstract: An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller.
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公开(公告)号：US20190187915A1
公开(公告)日：2019-06-20
申请号：US15847954
申请日：2017-12-20
Applicant: International Business Machines Corporation
Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary , John B. DeForge , Warren E. Maule , Kirk D. Peterson , Sridhar H. Rangarajan , Saravanan Sethuraman
Abstract: An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller.
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公开(公告)号：US20180358366A1
公开(公告)日：2018-12-13
申请号：US15807666
申请日：2017-11-09
Applicant: International Business Machines Corporation
Inventor： John B. DeForge , John J. Ellis-Monaghan , Terence B. Hook , Kirk D. Peterson
IPC: H01L27/1156
CPC classification number: H01L27/1156 , H01L27/11558 , H01L27/1211 , H01L29/42324
Abstract: A method fabricates a lateral non-volatile storage cell. The lateral non-volatile storage cell includes a first transistor including a first transistor body formed on a dielectric layer. The first transistor includes a source region and drain region on opposite sides of the first transistor body. A second transistor is laterally adjacent to the first transistor and includes a second transistor body, parallel with the first transistor body, formed on the dielectric layer. A first layer of gate oxide of a first thickness is formed over the first transistor body, and a second layer of gate oxide of a second thickness is formed over a portion of the second transistor body. The first thickness and the second thickness are different. A floating gate is formed over the first layer of gate oxide, the second layer of gate oxide, and the dielectric layer.
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公开(公告)号：US10153291B1
公开(公告)日：2018-12-11
申请号：US15807666
申请日：2017-11-09
Applicant: International Business Machines Corporation
Inventor： John B. DeForge , John J. Ellis-Monaghan , Terence B. Hook , Kirk D. Peterson
IPC: H01L27/115 , H01L27/1156 , H01L27/12 , H01L27/11558
CPC classification number: H01L27/1156 , H01L27/11558 , H01L27/1211 , H01L29/42324
Abstract: A method fabricates a lateral non-volatile storage cell. The lateral non-volatile storage cell includes a first transistor including a first transistor body formed on a dielectric layer. The first transistor includes a source region and drain region on opposite sides of the first transistor body. A second transistor is laterally adjacent to the first transistor and includes a second transistor body, parallel with the first transistor body, formed on the dielectric layer. A first layer of gate oxide of a first thickness is formed over the first transistor body, and a second layer of gate oxide of a second thickness is formed over a portion of the second transistor body. The first thickness and the second thickness are different. A floating gate is formed over the first layer of gate oxide, the second layer of gate oxide, and the dielectric layer.
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公开(公告)号：US09437670B2
公开(公告)日：2016-09-06
申请号：US13689090
申请日：2012-11-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Nathaniel R. Chadwick , John B. DeForge , John J. Ellis-Monaghan , Jeffrey P. Gambino , Ezra D. Hall , Marc D. Knox , Kirk D. Peterson
CPC classification number: H01L29/00 , G01R31/2818 , G01R31/2856 , H01L22/34 , H01L2924/0002 , H01L2924/00
Abstract: A test circuit including a light activated test connection in a semiconductor device is provided. The light activated test connection is electrically conductive during a test of the semiconductor device and is electrically non-conductive after the test.
Abstract translation: 提供一种包括半导体器件中的光激活测试连接的测试电路。 在半导体器件的测试期间，光激发测试连接是导电的，并且在测试之后是非导电的。
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