公开(公告)号：US20210305160A1

公开(公告)日：2021-09-30

申请号：US16828288

申请日：2020-03-24

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung CHEN ,  Chih-Chao YANG ,  Yann MIGNOT ,  Shanti PANCHARATNAM

IPC: H01L23/535 ,  H01L27/22 ,  H01L27/24 ,  H01L43/08 ,  H01L45/00 ,  H01L43/12 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device structure includes a memory element disposed within an interlayer dielectric (ILD) layer. A contact is disposed within the ILD in contact with the memory element and includes a first metal. A logic element is disposed within the ILD and comprises a second metal that is different than the first metal. A method of forming the semiconductor structure includes forming at least one memory element within an interlayer dielectric (ILD) layer. A contact that includes a first metal is formed in contact with the memory element. At least one logic element is formed in the ILD layer, where the logic element includes a second metal that is different than the first metal.

公开(公告)号：US20230197603A1

公开(公告)日：2023-06-22

申请号：US17645402

申请日：2021-12-21

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung CHEN ,  Su Chen FAN ,  Dechao GUO ,  Carl RADENS ,  Indira SESHADRI

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76877

Abstract: An interconnect layer for a device and methods for fabricating the interconnect layer are provided. The interconnect layer includes first metal structures arranged in a first array in the interconnect layer and second metal structures, arranged in a second array in the interconnect layer. The second array includes at least one metal structure positioned between two metal structures of the first metal structures. The interconnect layer also includes a spacer material formed around each of the first metal structures and the second metal structures and air gaps formed in the spacer material on each side of the first metal structures.

公开(公告)号：US20210320036A1

公开(公告)日：2021-10-14

申请号：US16847811

申请日：2020-04-14

Applicant: International Business Machines Corporation

Inventor： Nikhil JAIN ,  Hsueh-Chung CHEN ,  Mary Claire SILVESTRE ,  Hosadurga SHOBHA

IPC: H01L21/66 ,  G01N21/956 ,  G01N21/95 ,  G01B11/30 ,  G01B11/25

Abstract: A semiconductor structure and a method for managing semiconductor wafer stress are disclosed. The semiconductor structure includes a semiconductor wafer, a first stress layer disposed on and in contact with a backside of the semiconductor wafer, and a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second layer exerts a second stress on the semiconductor wafer that is opposite the first backside stress. The method includes forming a first stress layer on and in contact with a backside of a semiconductor wafer, and further forming a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second stress layer exerts a second stress on the semiconductor wafer that is opposite to the first stress.