-
公开(公告)号：US11276748B2
公开(公告)日：2022-03-15
申请号：US16527830
申请日：2019-07-31
发明人： Baozhen Li , Chih-Chao Yang , Andrew Tae Kim , Barry Linder
摘要： A switchable metal insulator metal capacitor (MIMcap) and a method for fabricating the MIMcap. In another aspect of the invention operating the MIMcap is also described. A first capacitor plate and a second capacitor plate are separated by a capacitor dielectric and disposed over a substrate. A first via is electrically connected to the first capacitor plate and comprised of phase change material (PCM). The PCM is deposited in an electrically conductive state and convertible by application of heat to an insulating state. A first heater is proximate to and electrically isolated from the PCM in the first via. When the first heater is activated it converts the PCM in the first via to the insulating state. This isolates the first capacitor plate from an integrated circuit.
-
公开(公告)号：US10971447B2
公开(公告)日：2021-04-06
申请号：US16450420
申请日：2019-06-24
发明人： Chih-Chao Yang , Baozhen Li , Andrew Tae Kim
IPC分类号： H01L23/52 , H01L23/48 , H01L27/11 , H01L23/525 , H01L27/112
摘要： An electrode structure is located at least partially in a via opening having a small feature size and containing a fuse element which is composed of a fuse element-containing seed layer that is subjected to a reflow anneal. The electrode structure is composed of a material having a higher electromigration (EM) resistance than the material that provides the fuse element. Prior to programming, the fuse element is present along sidewalls and a bottom wall of the electrode structure. After programming, a void is formed in the fuse element along at least one sidewall of the electrode structure and the resistance of the device will increase sharply.
-
公开(公告)号：US11647681B2
公开(公告)日：2023-05-09
申请号：US17060295
申请日：2020-10-01
发明人： Baozhen Li , Chih-Chao Yang , Andrew Tae Kim , Barry Linder
CPC分类号： H10N70/063 , H10B63/80 , H10N70/231 , H10N70/823 , H10N70/8413 , H10N70/8828
摘要： A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.
-
公开(公告)号：US10903117B2
公开(公告)日：2021-01-26
申请号：US16291463
申请日：2019-03-04
发明人： Baozhen Li , Chih-Chao Yang , Andrew Tae Kim
IPC分类号： H01L21/768 , H01L23/532 , H01L21/3213 , H01L23/522 , H01L23/528
摘要： An interconnection for a device in an integrated circuit includes a substrate on which a first metal line is embedded in a first dielectric layer. A via gouge is etched in the first metal line. A second dielectric layer is deposited over the first metal line and the first dielectric layer. A first via recess is etch through the second dielectric layer where the first via recess aligned to the via gouge. A second metal layer is deposited in the first via recess and the via gouge, forming a first via.
-
公开(公告)号：US20210020836A1
公开(公告)日：2021-01-21
申请号：US17060295
申请日：2020-10-01
发明人： Baozhen Li , Chih-Chao Yang , Andrew Tae Kim , Barry Linder
摘要： A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.
-
公开(公告)号：US10741441B2
公开(公告)日：2020-08-11
申请号：US16145733
申请日：2018-09-28
发明人： Baozhen Li , Chih-Chao Yang , Andrew Tae Kim
IPC分类号： H01L21/768 , H01L23/522
摘要： A via and a method of fabricating a via in an integrated circuit involve forming a trench in dielectric material deposited above a first cap of a first metal level. The method includes patterning a collar from insulator material directly above the first cap, and etching through the first cap, within an area surrounded by the collar, to a first metal layer of the first metal level directly below the first cap. A liner is conformally deposited. The liner lines sidewalls of the collar. A metal conductor is deposited to form the via and a second metal layer of a second metal level.
-
公开(公告)号：US20200126911A1
公开(公告)日：2020-04-23
申请号：US16167122
申请日：2018-10-22
发明人： Baozhen Li , Chih-Chao Yang , Andrew Tae Kim , Ernest Y Wu
IPC分类号： H01L23/525 , H01H85/08 , H01H85/143 , H01H69/02
摘要： A mandrel structure is provided over a dielectric using a patterning process. The mandrel structure includes a first mandrel, a second mandrel and a third mandrel in a parallel arrangement. The second mandrel is located between the first and third mandrels and has a cut larger than a minimum ground rule feature. A sidewall layer is formed over the mandrel structure. The sidewall layer has two long parallel gaps for two contact lines and a third gap for a fuse element. The third gap is orthogonal to and connects the two long parallel gaps. The mandrel structure is removed. The sidewall pattern is used to etch the dielectric to form a trench structure comprising two parallel contact line trenches having a width at least as great as a ground rule of the patterning process for the contact lines and a connecting, orthogonal fuse element trench having a width less than the ground rule for the fuse element. The trenches are filled with conductive material to form the contact lines and a fuse element. The contact lines function as an anode and a cathode in the e-Fuse.
-
公开(公告)号：US10770393B2
公开(公告)日：2020-09-08
申请号：US15925835
申请日：2018-03-20
发明人： Andrew Tae Kim , Baozhen Li , Ernest Y. Wu , Chih-Chao Yang
IPC分类号： H01L29/00 , H01L23/522 , H01L23/525 , H01L27/01 , H01L21/768 , H01L23/532
摘要： Back end of the line precision resistors that allow for high currents and for configuration as an eFuse by embedding a single thin film high resistive metal material within a dielectric layer, wherein the resisters are coupled to sidewalls of adjacent metal interconnects are described. The resistors can be formed in the metal one (M1) dielectric layer and can be coupled to sidewalls of the M1 interconnects. Also described are processes for fabricating integrated circuits including the resistors and/or e-Fuses.
-
公开(公告)号：US10651083B2
公开(公告)日：2020-05-12
申请号：US15911313
申请日：2018-03-05
发明人： Andrew Tae Kim , Baozhen Li , Ernest Y. Wu , Chih-Chao Yang
IPC分类号： H01L23/52 , H01L21/768 , H01L23/532
摘要： A graded cap is formed upon an interconnect, such as a back end of line wire. The graded cap includes a microstructure that uniformly changes from a metal nearest the interconnect to a metal nitride most distal from the interconnect. The graded cap is formed by nitriding a metal cap that is formed upon the interconnect. During nitriding an exposed one or more perimeter portions of the metal cap become a metal nitride with a larger amount or concentration of Nitrogen while one or more inner portions of the metal cap nearest the interconnect may be maintained as the metal or become the metal nitride with a fewer amount or concentration of Nitrogen. The resulting graded cap includes a gradually or uniformly changing microstructure between the one or more inner portions and the one or more perimeter portions.
-
公开(公告)号：US20190341347A1
公开(公告)日：2019-11-07
申请号：US15970601
申请日：2018-05-03
发明人： Baozhen Li , Chih-Chao Yang , Andrew Tae Kim
IPC分类号： H01L23/522 , H01L49/02 , H01L23/532 , H01L23/525 , H01L21/768
摘要： A method and structure to isolate BEOL MIM capacitors shorted or rendered highly leaky due to in process, or service induced defects, in a semiconductor chip are provided such that the rejection and loss of yield of otherwise good chips is minimized. In one embodiment, the method incorporates an isolation element such as, for example, a fuse, or a phase change material such as, a metal/insulation transition metal material, in series between the MIM capacitor and the active circuit. When a high current passes through the element due to the MIM capacitor being defective, the isolation element is rendered highly resistive or electrically open thereby disconnecting the defective capacitor or electrode plate from the active circuitry.
-
-
-
-
-
-
-
-
-
搜索结果
24 条记录 (耗时 0.019 秒)
