公开(公告)号：US12229867B2

公开(公告)日：2025-02-18

申请号：US18310015

申请日：2023-05-01

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Darrel Palke ,  Sherine Abdelhak ,  Jill Boyce ,  Varghese George ,  Scott Janus ,  Adam Lake ,  Zhijun Lei ,  Zhengmin Li ,  Mike MacPherson ,  Carl Marshall ,  Selvakumar Panneer ,  Prasoonkumar Surti ,  Karthik Veeramani ,  Deepak Vembar ,  Vallabhajosyula Srinivasa Somayazulu

IPC: G06T17/20 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/40

Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

公开(公告)号：US12101475B2

公开(公告)日：2024-09-24

申请号：US17127544

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Brinda Ganesh ,  Nilesh Jain ,  Sumit Mohan ,  Faouzi Kossentini ,  Jill Boyce ,  James Holland ,  Zhijun Lei ,  Chekib Nouira ,  Foued Ben Amara ,  Hassene Tmar ,  Sebastian Possos ,  Craig Hurst

IPC: H04N19/114 ,  H04N19/154

CPC classification number: H04N19/114 ,  H04N19/154

Abstract: Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.

公开(公告)号：US11151769B2

公开(公告)日：2021-10-19

申请号：US16537140

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Darrel Palke ,  Sherine Abdelhak ,  Jill Boyce ,  Varghese George ,  Scott Janus ,  Adam Lake ,  Zhijun Lei ,  Zhengmin Li ,  Mike Macpherson ,  Carl Marshall ,  Selvakumar Panneer ,  Prasoonkumar Surti ,  Karthik Veeramani ,  Deepak Vembar ,  Vallabhajosyula Srinivasa Somayazulu

IPC: G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06T17/20 ,  G06N3/08 ,  G06T15/40

Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

公开(公告)号：US11930159B2

公开(公告)日：2024-03-12

申请号：US16699243

申请日：2019-11-29

Applicant: Intel Corporation

Inventor： Jason Tanner ,  Zhijun Lei

IPC: H04N19/105 ,  H04N19/119 ,  H04N19/142 ,  H04N19/176 ,  H04N19/426

CPC classification number: H04N19/105 ,  H04N19/119 ,  H04N19/142 ,  H04N19/176 ,  H04N19/427

Abstract: Methods, articles, and systems of video coding use intra block copying with hash-based searches.

公开(公告)号：US10951900B2

公开(公告)日：2021-03-16

申请号：US16015758

申请日：2018-06-22

Applicant: INTEL CORPORATION

Inventor： Zhijun Lei ,  Jason Tanner ,  Satya N. Yedidi

IPC: H04N19/159 ,  H04N19/124 ,  H04N19/176 ,  H04N19/436 ,  H04N19/122 ,  H04N19/46 ,  H04N19/11 ,  H04N19/157

Abstract: Speeding up small block intra-prediction in video coding is described herein. The system includes an encoder. The encoder is to execute intra-prediction by deriving a plurality of prediction angles, wherein the prediction angles are based on a video coding standard. The encoder is also to disable a prediction angle for a current block to eliminate a dependency on an immediate predecessor block.

公开(公告)号：US20200099926A1

公开(公告)日：2020-03-26

申请号：US16699243

申请日：2019-11-29

Applicant: Intel Corporation

Inventor： Jason Tanner ,  Zhijun Lei

IPC: H04N19/105 ,  H04N19/119 ,  H04N19/426 ,  H04N19/142 ,  H04N19/176

Abstract: Methods, articles, and systems of video coding use intra block copying with hash-based searches.

公开(公告)号：US12047575B2

公开(公告)日：2024-07-23

申请号：US17539099

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Alexander Alshin ,  Jill Boyce ,  Zhijun Lei ,  Miroslav Goncharenko ,  Vasily Aristarkhov

IPC: H04N19/13 ,  H04N19/176 ,  H04N19/196 ,  H04N19/91

CPC classification number: H04N19/13 ,  H04N19/176 ,  H04N19/196 ,  H04N19/91

Abstract: Methods, apparatus, systems, and articles of manufacture for multi-symbol equiprobable mode entropy coding, An example apparatus includes equiprobabie bypass control circuitry to determine whether an input value associated with the one or more blocks is greater than a reference value. The example apparatus also includes interval control circuitry to, based on the determination, adjust at least one of an upper limit or a lower limit based on an approximate value approximating a product of (1) a quotient of (a) a difference between the alphabet size and one and (b) the alphabet size and (2) the upper limit, the upper limit and the lower limit forming a range of values within which the input value is to be encoded.

公开(公告)号：US20220109840A1

公开(公告)日：2022-04-07

申请号：US17555092

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Ximin Zhang ,  Zhijun Lei ,  Jill Boyce ,  Sang-Hee Lee

IPC: H04N19/126 ,  H04N19/70 ,  H04N19/423 ,  H04N19/119 ,  H04N19/172 ,  H04N19/18 ,  H04N19/136

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to encode and decode video using quantization matrices. An example apparatus includes interface circuitry to access an input frame of video, quantization matrix syntax encoder circuitry to encode a set of user-defined quantization matrices into a sequence header associated with a sequence of video frames including the input frame, adaptive quantization matrix selector circuitry to select a subset of quantization matrices from a combination of a set of default quantization matrices and the set of user-defined quantization matrices, adaptive segment selector circuitry to select a first one of the subset of quantization matrices for a first segment of the input frame, the input frame to be divided into a plurality of segments including the first segment, and encoder circuitry to quantize transform coefficients of the first segment of the input frame based on the first one of the subset of quantization matrices.

公开(公告)号：US20220086445A1

公开(公告)日：2022-03-17

申请号：US17539099

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Alexander Alshin ,  Jill Boyce ,  Zhijun Lei ,  Miroslav Goncharenko ,  Vasily Aristarkhov

IPC: H04N19/13 ,  H04N19/91 ,  H04N19/196 ,  H04N19/176

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for multi-symbol equiprobable mode entropy coding. An example apparatus includes equiprobable bypass control circuitry to determine whether an input value associated with the one or more blocks is greater than a reference value. The example apparatus also includes interval control circuitry to, based on the determination, adjust at least one of an upper limit or a lower limit based on an approximate value approximating a product of (1) a quotient of (a) a difference between the alphabet size and one and (b) the alphabet size and (2) the upper limit, the upper limit and the lower limit forming a range of values within which the input value is to be encoded.

公开(公告)号：US20190045186A1

公开(公告)日：2019-02-07

申请号：US15994017

申请日：2018-05-31

Applicant: Intel Corporation

Inventor： Ximin Zhang ,  Sang-hee Lee ,  Zhijun Lei ,  Dmitry Ryzhov

IPC: H04N19/117 ,  H04N19/124 ,  H04N19/86 ,  H04N19/172

Abstract: Techniques related to selecting constrained directional enhancement filters for video coding are discussed. Such techniques may include selecting subset of constrained directional enhancement filters for use by a frame based on a frame level quantization parameter of the frame such that only the subset is used for filtering the frame.