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公开(公告)号：US11277903B2
公开(公告)日：2022-03-15
申请号：US16368221
申请日：2019-03-28
申请人： Intel Corporation
IPC分类号： H05K3/02 , H05K1/02 , G05B19/4097 , H05K1/18
摘要： Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
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公开(公告)号：US11729900B2
公开(公告)日：2023-08-15
申请号：US17694201
申请日：2022-03-14
申请人： Intel Corporation
IPC分类号： H05K1/02 , G05B19/4097 , H05K3/02 , H05K1/18
CPC分类号： H05K1/0225 , G05B19/4097 , H05K3/027 , G05B2219/45026 , G05B2219/45034 , H05K1/18 , H05K2201/093 , H05K2201/098 , H05K2201/09027 , H05K2201/10098
摘要： Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
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公开(公告)号：US20210191512A1
公开(公告)日：2021-06-24
申请号：US17195057
申请日：2021-03-08
申请人： Intel Corporation
摘要： Apparatus, systems, articles of manufacture, and methods for adaptive display control in virtual reality environments are disclosed. An example virtual reality display device for adaptive display control in a virtual reality environment includes memory and a processor to execute instructions to detect a first pupil size after a predetermined amount of time, determine a characteristic of a display image, identify a second pupil size from a plurality of pupil sizes correlated with the characteristic of the display image, perform a comparison of the first pupil size and the second pupil size, determine a margin of difference between the first pupil size and the second pupil size, and adjust the characteristic of the display image to change the first pupil size and reduce the margin difference.
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公开(公告)号：US20190265785A1
公开(公告)日：2019-08-29
申请号：US16222363
申请日：2018-12-17
申请人： Intel Corporation
摘要： Apparatus, systems, articles of manufacture, and methods for adaptive display control in virtual reality environments are disclosed. An example virtual reality display device for adaptive display control in a virtual reality environment includes a scanner to detect a first size of a pupil of an eye of a user. The device also includes an analyzer to determine a first characteristic of a display image, reference a second pupil size based on the first characteristic of the display image, compare the first pupil size and the second pupil size, and adjust a second characteristic of the display image when the second pupil size is different than the first pupil size. The device also includes a display screen to present the second characteristic.
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公开(公告)号：US11955436B2
公开(公告)日：2024-04-09
申请号：US16393304
申请日：2019-04-24
申请人： Intel Corporation
发明人： Khang Choong Yong , Ying Ern Ho , Yun Rou Lim , Wil Choon Song , Stephen Hall
IPC分类号： H01L23/552 , H01L23/00 , H01L23/66 , H05K1/02
CPC分类号： H01L23/552 , H01L23/66 , H01L24/17 , H05K1/0216 , H05K1/025 , H01L2223/6627
摘要： Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.
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公开(公告)号：US20230396025A1
公开(公告)日：2023-12-07
申请号：US18454487
申请日：2023-08-23
申请人： Intel Corporation
发明人： Ying Ern Ho , Boon Ping Koh , Ya Yeing Lo , Luqman Al-Hakim Mohd Nasran , Ameera Wahida Solikhudin
IPC分类号： H01R13/6596 , H01B7/17 , H01R13/26
CPC分类号： H01R13/6596 , H01B7/17 , H01R13/26
摘要： A magnetic grounding technique implements a magnet assembly. The magnet assembly may be soldered to a component to facilitate grounding of a metal shield layer of a cable assembly. A cable plating may be plated onto an exposed part of the insulator of a cable assembly to form the cable assembly, and which galvanically contacts the metal shield layer of the cable assembly. The cable plating may comprise an electrically conductive and magnetic material to ensure magnetic attraction with the magnet assembly. The magnetic assembly is thus magnetically attracted to the cable plating, and also provides galvanic contact between the cable plating and, in turn, the metal shield layer of the cable and ground to reduce RFI. The magnet assembly also magnetically aligns the cable connection pins with those of a mating connector, thus reducing the strain placed on the connectors.
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公开(公告)号：US20180122748A1
公开(公告)日：2018-05-03
申请号：US15335999
申请日：2016-10-27
申请人： Intel Corporation
发明人： Hao-Han Hsu , Ying Ern Ho , Jaejin Lee
CPC分类号： H01L23/562 , H01L23/498 , H01L23/552 , H01L23/66 , H01L2223/6644 , H01L2223/6677
摘要： Embodiments herein may relate to a package with one or more layers. A silicon die may be coupled with the one or more layers via an adhesive. A package stiffener may also be coupled with the adhesive adjacent to the die. A magnetic thin film may be coupled with the package stiffener. Other embodiments may be described and/or claimed.
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公开(公告)号：US20220304143A1
公开(公告)日：2022-09-22
申请号：US17694201
申请日：2022-03-14
申请人： Intel Corporation
IPC分类号： H05K1/02 , G05B19/4097 , H05K3/02
摘要： Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
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公开(公告)号：US10942565B2
公开(公告)日：2021-03-09
申请号：US16222363
申请日：2018-12-17
申请人： Intel Corporation
摘要： Apparatus, systems, articles of manufacture, and methods for adaptive display control in virtual reality environments are disclosed. An example virtual reality display device for adaptive display control in a virtual reality environment includes a scanner to detect a first size of a pupil of an eye of a user. The device also includes an analyzer to determine a first characteristic of a display image, reference a second pupil size based on the first characteristic of the display image, compare the first pupil size and the second pupil size, and adjust a second characteristic of the display image when the second pupil size is different than the first pupil size. The device also includes a display screen to present the second characteristic.
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公开(公告)号：US10779402B1
公开(公告)日：2020-09-15
申请号：US16402992
申请日：2019-05-03
申请人： Intel Corporation
发明人： Kai Chong Ng , Natasya Athirah Abdul Khalid , Florence Su Sin Phun , Yee Hung See Tau , Asmah Truky , Ying Ern Ho
IPC分类号： H05K1/02 , H01L23/498 , G06F1/10
摘要： A printed circuit board (PCB) includes a dielectric plane and a ground plane parallel to and spaced apart from the dielectric plane. The dielectric plane includes a pair of signal traces and a 3-dimensional (3D) grounded (GND) fence located between the pair of signal traces. The 3D GND fence is electrically connected to the ground plane, and protrudes perpendicularly from the dielectric plane. The 3D GND fence is located equidistant from each of the pair of signal traces, and the 3D GND fence is configured to block electromagnetic interference (EMI) from a first of the pair of signal traces to a second of the pair of the signal traces. The pair of signal traces is configured to form part of a noise-sensitive electronic circuit. The 3D GND fence may have a rectangular configuration.
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