公开(公告)号：US11256626B2

公开(公告)日：2022-02-22

申请号：US16837833

申请日：2020-04-01

Applicant: Intel Corporation

Inventor： Wim Heirman ,  Ibrahim Hur ,  Ugonna Echeruo ,  Stijn Eyerman ,  Kristof Du Bois

IPC: G06F12/08 ,  G06F12/0862

Abstract: Apparatus, method, and system for enhancing data prefetching based on non-uniform memory access (NUMA) characteristics are described herein. An apparatus embodiment includes a system memory, a cache, and a prefetcher. The system memory includes multiple memory regions, at least some of which are associated with different NUMA characteristic (access latency, bandwidth, etc.) than others. Each region is associated with its own set of prefetch parameters that are set in accordance to their respective NUMA characteristics. The prefetcher monitors data accesses to the cache and generates one or more prefetch requests to fetch data from the system memory to the cache based on the monitored data accesses and the set of prefetch parameters associated with the memory region from which data is to be fetched. The set of prefetcher parameters may include prefetch distance, training-to-stable threshold, and throttle threshold.

公开(公告)号：US20200174929A1

公开(公告)日：2020-06-04

申请号：US16203891

申请日：2018-11-29

Applicant: Intel Corporation

Inventor： Wim Heirman ,  Stijn Eyerman ,  Kristof Du Bois ,  Ibrahim Hur ,  Joshua B. Fryman

IPC: G06F12/0804

Abstract: In one embodiment, an apparatus includes a memory access circuit to receive memory access instructions and provide at least some of the memory access instructions to a memory subsystem for execution. The memory access circuit may have a conversion circuit to convert the first memory access instruction to a first subline memory access instruction, e.g., based at least in part on an access history for a first memory access instruction. Other embodiments are described and claimed.

公开(公告)号：US10684858B2

公开(公告)日：2020-06-16

申请号：US15996184

申请日：2018-06-01

Applicant: Intel Corporation

Inventor： Stijn Eyerman ,  Wim Heirman ,  Kristof Du Bois ,  Ibrahim Hur ,  Joshua B. Fryman

IPC: G06F9/38 ,  G06F9/30

Abstract: Disclosed embodiments relate to an indirect memory fetch (IMF) unit. In one example, an apparatus includes circuitry to fetch and decode an instruction specifying a sparse operand array including N operands, and an index array including N contiguously-addressed indices. The apparatus further includes a processing engine associated with an IMF unit to respond to the decoded instruction by initializing the IMF unit to fetch the N operands in order, probing the IMF unit to determine that a fetched operand is ready to retrieve, retrieving the fetched operand from the IMF unit, and repeating the probing and retrieving until all N operands have been retrieved. The IMF unit, independent of the processing engine, is to fetch the N contiguously-addressed indices from the index array, use the N fetched indices to calculate memory addresses for the N operands, and issue a plurality of read requests to fetch the N operands in order.

公开(公告)号：US20190095333A1

公开(公告)日：2019-03-28

申请号：US15718845

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Wim Heirman ,  Kristof Du Bois ,  Yves Vandriessche ,  Stijn Eyerman ,  Ibrahim Hur

IPC: G06F12/0862 ,  G06F5/14

Abstract: Embodiments of apparatuses, methods, and systems for independent tuning of multiple hardware prefetchers are described. In an embodiment, an apparatus includes a processor core, a cache memory, a hardware prefetcher, and a prefetch tuner. The hardware prefetcher is to prefetch data for the processor core from a system memory to the cache memory. The prefetch tuner is to adjust a prefetch rate of the hardware prefetcher based on a fraction of late prefetches. The prefetch tuner includes a late prefetch counter to count a number of late prefetches for the hardware prefetcher, a prefetch counter to count a number of prefetches for the hardware prefetcher, and a late prefetch calculator to calculate the fraction of late prefetches based on the number of late prefetches and the number of prefetches.

公开(公告)号：US11526483B2

公开(公告)日：2022-12-13

申请号：US15941262

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Stijn Eyerman ,  Jason M. Howard ,  Ibrahim Hur ,  Ivan B. Ganev ,  Fabrizio Petrini ,  Joshua B. Fryman

IPC: G06F16/00 ,  G06F16/22 ,  G06F16/901

Abstract: Methods, apparatus, systems and articles of manufacture to build a storage architecture for graph data are disclosed herein. Disclosed example apparatus include a neighbor identifier to identify respective sets of neighboring vertices of a graph. The neighboring vertices included in the respective sets are adjacent to respective ones of a plurality of vertices of the graph and respective sets of neighboring vertices are represented as respective lists of neighboring vertex identifiers. The apparatus also includes an element creator to create, in a cache memory, an array of elements that are unpopulated. The array elements have lengths equal to a length of a cache line. In addition, the apparatus includes an element populater to populate the elements with neighboring vertex identifiers. Each of the elements store neighboring vertex identifiers of respective ones of the list of neighboring vertex identifiers.

公开(公告)号：US20220229677A1

公开(公告)日：2022-07-21

申请号：US17712094

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： Wim Heirman ,  Stijn Eyerman ,  Kristof Du Bois ,  Ibrahim Hur

IPC: G06F9/455 ,  G06F9/52

Abstract: A distributed simulation system is provided that includes a timing simulator and functional simulator(s) on different computing nodes to simulate a graph processing system. The functional simulators are to simulate execution of a set of instructions on the graph processing system and to send information associated with the simulated set of instructions to the timing simulator over the network. The timing simulator is to determine timing information associated with execution of the sets of instructions sent by the functional simulators and send the timing information to the functional simulators over the network. The timing simulator may determine a global synchronization point for the functional simulators and send the timing information for the sets of instructions to respective functional simulators at the global synchronization point. The functional simulators may stall simulation of further instructions until the timing information for its set of instructions is received from the timing simulator.

公开(公告)号：US20190042613A1

公开(公告)日：2019-02-07

申请号：US15941262

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Stijn Eyerman ,  Jason M. Howard ,  Ibrahim Hur ,  Ivan B. Ganev ,  Fabrizio Petrini ,  Joshua B. Fryman

IPC: G06F17/30

Abstract: Methods, apparatus, systems and articles of manufacture to build a storage architecture for graph data are disclosed herein. Disclosed example apparatus include a neighbor identifier to identify respective sets of neighboring vertices of a graph. The neighboring vertices included in the respective sets are adjacent to respective ones of a plurality of vertices of the graph and respective sets of neighboring vertices are represented as respective lists of neighboring vertex identifiers. The apparatus also includes an element creator to create, in a cache memory, an array of elements that are unpopulated. The array elements have lengths equal to a length of a cache line. In addition, the apparatus includes an element populater to populate the elements with neighboring vertex identifiers. Each of the elements store neighboring vertex identifiers of respective ones of the list of neighboring vertex identifiers.

公开(公告)号：US20230418612A1

公开(公告)日：2023-12-28

申请号：US17848284

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Kristof Du Bois ,  Wim Heirman ,  Stijn Eyerman ,  Ibrahim Hur ,  Jason Agron

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F9/30036

Abstract: Techniques for automatic fusion of arithmetic in-flight instructions are described. An example apparatus comprises a buffer to store instructions to be issued to a functional unit for execution, and circuitry coupled to the buffer to combine two or more instructions from the buffer into a single combined instruction. Other examples are disclosed and claimed.

公开(公告)号：US10942851B2

公开(公告)日：2021-03-09

申请号：US16203891

申请日：2018-11-29

Applicant: Intel Corporation

Inventor： Wim Heirman ,  Stijn Eyerman ,  Kristof Du Bois ,  Ibrahim Hur ,  Joshua B. Fryman

IPC: G06F12/08 ,  G06F12/0804

Abstract: In one embodiment, an apparatus includes a memory access circuit to receive memory access instructions and provide at least some of the memory access instructions to a memory subsystem for execution. The memory access circuit may have a conversion circuit to convert the first memory access instruction to a first subline memory access instruction, e.g., based at least in part on an access history for a first memory access instruction. Other embodiments are described and claimed.

公开(公告)号：US20200233806A1

公开(公告)日：2020-07-23

申请号：US16837833

申请日：2020-04-01

Applicant: Intel Corporation

Inventor： Wim Heirman ,  Ibrahim Hur ,  Ugonna Echeruo ,  Stijn Eyerman ,  Kristof Du Bois

IPC: G06F12/0862

Abstract: Apparatus, method, and system for enhancing data prefetching based on non-uniform memory access (NUMA) characteristics are described herein. An apparatus embodiment includes a system memory, a cache, and a prefetcher. The system memory includes multiple memory regions, at least some of which are associated with different NUMA characteristic (access latency, bandwidth, etc.) than others. Each region is associated with its own set of prefetch parameters that are set in accordance to their respective NUMA characteristics. The prefetcher monitors data accesses to the cache and generates one or more prefetch requests to fetch data from the system memory to the cache based on the monitored data accesses and the set of prefetch parameters associated with the memory region from which data is to be fetched. The set of prefetcher parameters may include prefetch distance, training-to-stable threshold, and throttle threshold.