公开(公告)号：US20190205737A1

公开(公告)日：2019-07-04

申请号：US15859504

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Anavai Ramesh ,  Asit Mishra ,  Deborah Marr ,  Jeffrey Cook ,  Srinivas Sridharan ,  Eriko Nurvitadhi ,  Elmoustapha Ould-Ahmed-Vall ,  Dheevatsa Mudigere ,  Mohammad Ashraf Bhuiyan ,  Md Faijul Amin ,  Wei Wang ,  Dhawal Srivastava ,  Niharika Maheshwari

IPC: G06N3/063 ,  G06N3/08 ,  G06F7/78 ,  G06T1/20

CPC classification number: G06N3/063 ,  G06F7/78 ,  G06N3/084 ,  G06T1/20

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

公开(公告)号：US12039435B2

公开(公告)日：2024-07-16

申请号：US17845794

申请日：2022-06-21

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Anavai Ramesh ,  Asit Mishra ,  Deborah Marr ,  Jeffrey Cook ,  Srinivas Sridharan ,  Eriko Nurvitadhi ,  Elmoustapha Ould-Ahmed-Vall ,  Dheevatsa Mudigere ,  Mohammad Ashraf Bhuiyan ,  Md Faijul Amin ,  Wei Wang ,  Dhawal Srivastava ,  Niharika Maheshwari

IPC: G06N3/063 ,  G06F7/78 ,  G06F9/00 ,  G06N3/084 ,  G06N20/00 ,  G06T1/20

CPC classification number: G06N3/063 ,  G06F7/78 ,  G06F9/00 ,  G06N3/084 ,  G06N20/00 ,  G06F2207/4824 ,  G06T1/20

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

公开(公告)号：US11373088B2

公开(公告)日：2022-06-28

申请号：US15859504

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Anavai Ramesh ,  Asit Mishra ,  Deborah Marr ,  Jeffrey Cook ,  Srinivas Sridharan ,  Eriko Nurvitadhi ,  Elmoustapha Ould-Ahmed-Vall ,  Dheevatsa Mudigere ,  Mohammad Ashraf Bhuiyan ,  Md Faijul Amin ,  Wei Wang ,  Dhawal Srivastava ,  Niharika Maheshwari

IPC: G06N3/063 ,  G06N20/00 ,  G06F7/78 ,  G06N3/08 ,  G06F9/00 ,  G06T1/20

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

公开(公告)号：US20240403620A1

公开(公告)日：2024-12-05

申请号：US18679802

申请日：2024-05-31

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Anavai Ramesh ,  Asit Mishra ,  Deborah Marr ,  Jeffrey Cook ,  Srinivas Sridharan ,  Eriko Nurvitadhi ,  Elmoustapha Ould-Ahmed-Vall ,  Dheevatsa Mudigere ,  Mohammad Ashraf Bhuiyan ,  Md Faijul Amin ,  Wei Wang ,  Dhawal Srivastava ,  Niharika Maheshwari

IPC: G06N3/063 ,  G06F7/78 ,  G06F9/00 ,  G06N3/084 ,  G06N20/00 ,  G06T1/20

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

公开(公告)号：US20230053289A1

公开(公告)日：2023-02-16

申请号：US17845794

申请日：2022-06-21

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Anavai Ramesh ,  Asit Mishra ,  Deborah Marr ,  Jeffrey Cook ,  Srinivas Sridharan ,  Eriko Nurvitadhi ,  Elmoustapha Ould-Ahmed-Vall ,  Dheevatsa Mudigere ,  Mohammad Ashraf Bhuiyan ,  Md Faijul Amin ,  Wei Wang ,  Dhawal Srivastava ,  Niharika Maheshwari

IPC: G06N3/063 ,  G06F7/78 ,  G06N3/08 ,  G06N20/00 ,  G06F9/00

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

公开(公告)号：US10891131B2

公开(公告)日：2021-01-12

申请号：US15273146

申请日：2016-09-22

Applicant: Intel Corporation

Inventor： Mohammad Ashraf Bhuiyan ,  Brian R. Nickerson

IPC: G06F9/30 ,  G06F13/40 ,  G06F15/80

Abstract: A decode unit to decode an instruction that indicates a source packed data that includes data elements, and indicates a source mask that includes mask elements. Each of the mask elements corresponds to a different one of the data elements. Each of the mask elements is one of a masked mask element and an unmasked mask element. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result packed data. When the source packed data includes one or more masked data elements disposed within unmasked data elements, the result packed data includes, the unmasked data elements consolidated together without the one or more masked data elements disposed within them. The execution unit, is to store a result in a second destination storage location that reflects a number of the unmasked data elements consolidated together.