公开(公告)号：US20190294570A1

公开(公告)日：2019-09-26

申请号：US16442094

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： Jasvinder Singh ,  Harry van Haaren ,  Reshma Pattan ,  Radu Nicolau

IPC: G06F13/28 ,  G06F9/54 ,  H04L12/883

Abstract: Technologies for dynamic multi-core packet processing distribution include a compute device having a distributor core, a direct memory access (DMA) engine, and multiple worker cores. The distributor core writes work data to a distribution buffer. The work data is associated with a packet processing operation. The distributor core may perform a work distribution operation to generate the work data. The work data may be written to a private cache of the distributor core. The distributor core programs the DMA engine to copy the work data from the distribution buffer to a shadow buffer. The DMA engine may copy the work data from one cache line of a shared cache to another cache line of the shared cache. The worker cores access the work data in the shadow buffer. The worker cores may perform the packet processing operation with the work data. Other embodiments are described and claimed.

公开(公告)号：US20180097728A1

公开(公告)日：2018-04-05

申请号：US15353329

申请日：2016-11-16

Applicant: Intel Corporation

Inventor： Bhanu Prakash Bodi Reddy ,  Jasvinder Singh ,  Antonio Fischetti

IPC: H04L12/741 ,  H04L12/931 ,  H04L12/747 ,  H04L12/725

CPC classification number: H04L45/745 ,  H04L45/742 ,  H04L49/70

Abstract: A virtual switch configured to switch packets between virtual switch ports based on classifier sub-tables. The virtual switch reserves blocks of last level cache for classifier sub-table storage. The virtual switch also maintains a global sub-table priority map for the classifier sub-tables. The global sub-table priority map indicates usage frequency of each classifier sub-table when switching the packets between the ports. A sub-set of the classifier sub-tables with a highest usage frequency, according to the global sub-table priority map, are pre-fetched to the reserved blocks of the last level cache. By pre-fetching the most used classifier sub-tables, memory related bottlenecks are reduced when searching through classifier sub-tables. This mechanism increases processing speed when matching packets/flows to classifier sub-tables, resulting in faster packet switching by the virtual switch. The virtual switch may leverage Cache Allocation Technology (CAT)/Code and Data Prioritization technology (CDP) to prevent cache eviction.

公开(公告)号：US11431565B2

公开(公告)日：2022-08-30

申请号：US16160176

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Mohammad Abdul Awal ,  Jasvinder Singh ,  Reshma Pattan ,  David Hunt ,  Declan Doherty ,  Chris Macnamara

IPC: H04L41/0816 ,  H04L49/90 ,  H04L43/16 ,  H04L43/0894 ,  H04L49/00 ,  H04L43/10

Abstract: Examples include techniques for monitoring a data packet transfer rate at an interface queue, and based at least in part on a comparison of the data packet transfer rate to a threshold, assigning the interface queue from a core of a first class to a core of a second class or assigning the interface queue from a core of the second class to a core of the first class.

公开(公告)号：US11057306B2

公开(公告)日：2021-07-06

申请号：US16353730

申请日：2019-03-14

Applicant: Intel Corporation

Inventor： Jasvinder Singh ,  John J. Browne ,  Shobhi Jain ,  Sunku Ranganath ,  John O'Loughlin ,  Emma L. Foley

IPC: H04L12/803 ,  G06F9/445 ,  H04L12/851 ,  H04L12/801 ,  H04L12/823 ,  H04L12/859 ,  H04L12/813

Abstract: Examples include a method of determining a first traffic overload protection policy for a first service provided by a first virtual network function in a network of virtual network functions in a computing system and determining a second traffic overload protection policy for a second service provided by a second virtual network function in the network of virtual network functions. The method includes applying the first traffic overload protection policy to the first virtual network function and the second traffic overload protection policy to the second virtual network function, wherein the first traffic overload protection policy and the second traffic overload protection policy are different.

公开(公告)号：US10354033B2

公开(公告)日：2019-07-16

申请号：US15711740

申请日：2017-09-21

Applicant: Intel Corporation

Inventor： Cristian Florin Dumitrescu ,  Jasvinder Singh ,  Patrick Lu

IPC: G06F17/50 ,  G06F9/54 ,  G06F9/50 ,  H04L29/06

Abstract: One embodiment provides a system to identify a “best” usage of a given set of CPU cores to maximize performance of a given application. The given application is parsed into a number of functional blocks, and the system maps the functional blocks to the given set of CPU cores to maximize the performance of the given application. The system determines and then tests various mappings to determine the performance, generally preferring mappings that maximize throughput per physical core. Before testing a mapping, the system determines whether the mapping is redundant with any previously tested mappings. In addition, given a performance target for the given application, the system determines a minimum number of CPU cores needed for the application to meet the application performance target.

公开(公告)号：US11805065B2

公开(公告)日：2023-10-31

申请号：US16287339

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Jasvinder Singh ,  John J. Browne ,  Tomasz Kantecki ,  Chris Macnamara

IPC: H04W72/12 ,  H04L47/50 ,  H04L47/60 ,  H04L47/52 ,  H04L47/62 ,  H04L47/80 ,  H04L49/90 ,  H04L47/74 ,  H04L47/525 ,  H04L1/1867 ,  H04W72/1263 ,  H04L1/1829 ,  H04W52/02 ,  H04J3/08 ,  H04L12/437 ,  H04W52/26 ,  H04L41/5009 ,  H04L12/40

CPC classification number: H04L47/58 ,  H04L1/1854 ,  H04L1/1887 ,  H04L47/522 ,  H04L47/525 ,  H04L47/60 ,  H04L47/6215 ,  H04L47/74 ,  H04L47/805 ,  H04L47/808 ,  H04L49/9031 ,  H04W52/0216 ,  H04W72/12 ,  H04W72/1263 ,  H04J3/085 ,  H04L12/4015 ,  H04L12/437 ,  H04L41/5012 ,  H04W52/265

Abstract: Packets are differentiated based on their traffic class. A traffic class is allocated bandwidth for transmission. One or more core or thread can be allocated to process packets of a traffic class for transmission based on allocated bandwidth for that traffic class. If multiple traffic classes are allocated bandwidth, and a traffic class underutilizes allocated bandwidth or a traffic class is allocated insufficient bandwidth, then allocated bandwidth can be adjusted for a future transmission time slot. For example, a higher priority traffic class with excess bandwidth can share the excess bandwidth with a next highest priority traffic class for use to allocate packets for transmission for the same time slot. In the same or another example, bandwidth allocated to a traffic class depends on an extent of insufficient allocation or underutilization of allocated bandwidth such that a traffic class with insufficient allocated bandwidth in one or more prior time slot can be provided more bandwidth in a current time slot and a traffic class with underutilization of allocated bandwidth can be provided with less allocated bandwidth for a current time slot.

公开(公告)号：US20210075732A1

公开(公告)日：2021-03-11

申请号：US16953210

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Jasvinder Singh ,  Thomas Long ,  Eoin Walsh ,  John J. Browne

IPC: H04L12/851 ,  H04L12/865 ,  H04L12/869 ,  H04L12/863 ,  H04L12/927

Abstract: In one embodiment, a system comprises an interface to receive a plurality of packets; and a plurality of processor units to execute a plurality of transmission sub-interfaces, each transmission sub-interface to perform hierarchical quality of service (HQoS) scheduling on a distinct subset of the plurality of packets, wherein each transmission sub-interface is to schedule its subset of the plurality of packets for transmission by a network interface controller by assigning the packets of the subset to a plurality of transmission queues that each correspond to a distinct traffic class.

公开(公告)号：US10932202B2

公开(公告)日：2021-02-23

申请号：US16442094

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： Jasvinder Singh ,  Harry van Haaren ,  Reshma Pattan ,  Radu Nicolau

IPC: G06F13/28 ,  G06F9/54 ,  H04L12/861 ,  H04W28/00 ,  H04W52/24 ,  H04W24/10 ,  H04B17/336 ,  H04W72/04 ,  H04L1/00 ,  H04L12/883 ,  H04W52/36 ,  H04W52/42 ,  H04B7/0413

Abstract: Technologies for dynamic multi-core packet processing distribution include a compute device having a distributor core, a direct memory access (DMA) engine, and multiple worker cores. The distributor core writes work data to a distribution buffer. The work data is associated with a packet processing operation. The distributor core may perform a work distribution operation to generate the work data. The work data may be written to a private cache of the distributor core. The distributor core programs the DMA engine to copy the work data from the distribution buffer to a shadow buffer. The DMA engine may copy the work data from one cache line of a shared cache to another cache line of the shared cache. The worker cores access the work data in the shadow buffer. The worker cores may perform the packet processing operation with the work data. Other embodiments are described and claimed.

公开(公告)号：US10187308B2

公开(公告)日：2019-01-22

申请号：US15353329

申请日：2016-11-16

Applicant: Intel Corporation

Inventor： Bhanu Prakash Bodi Reddy ,  Jasvinder Singh ,  Antonio Fischetti

IPC: H04L12/725 ,  H04L12/741 ,  H04L12/747 ,  H04L12/931

Abstract: A virtual switch configured to switch packets between virtual switch ports based on classifier sub-tables. The virtual switch reserves blocks of last level cache for classifier sub-table storage. The virtual switch also maintains a global sub-table priority map for the classifier sub-tables. The global sub-table priority map indicates usage frequency of each classifier sub-table when switching the packets between the ports. A sub-set of the classifier sub-tables with a highest usage frequency, according to the global sub-table priority map, are pre-fetched to the reserved blocks of the last level cache. By pre-fetching the most used classifier sub-tables, memory related bottlenecks are reduced when searching through classifier sub-tables. This mechanism increases processing speed when matching packets/flows to classifier sub-tables, resulting in faster packet switching by the virtual switch. The virtual switch may leverage Cache Allocation Technology (CAT)/Code and Data Prioritization technology (CDP) to prevent cache eviction.