公开(公告)号：US20040119147A1

公开(公告)日：2004-06-24

申请号：US10329210

申请日：2002-12-23

Applicant: Intel Corporation

Inventor： Weston Roth ,  Damion T. Searls ,  James D. Jackson

IPC: H01L023/495

CPC classification number: H01L23/642 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K1/162 ,  H05K3/02 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2203/0315 ,  H05K2203/0796 ,  H05K2203/095 ,  H05K2203/1142 ,  H01L2924/00

Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.

Abstract translation: 本发明涉及一种用于改善相邻信号迹线之间以及平面分裂之间的交流耦合的装置和方法以及跨越电路板上的平面分裂的信号。 电路板包括相邻的导电装置和插入其间的氧化物装置。 氧化物是氧化铜，例如铜或氧化亚铜。 在一个实施例中，相邻的导电装置是相邻的电压参考平面，其间插入在导电装置之间。 氧化铜填充分流。 在另一个实施例中，相邻的导电装置是差分信号迹线。 氧化铜填充差分信号迹线之间的间隙。 与用作填料的其它常用绝缘材料相比，氧化铜是一种具有增加的介电常数的非导电材料。 增加的介电常数增加了电容，进而增加了交流耦合。

公开(公告)号：US20040005736A1

公开(公告)日：2004-01-08

申请号：US10187513

申请日：2002-07-02

Applicant: Intel Corporation

Inventor： Damion T. Searls ,  Terrance J. Dishongh ,  James Daniel Jackson

IPC: H01L021/44 ,  H01L023/34

CPC classification number: H01L23/433 ,  B82Y10/00 ,  H01L23/373 ,  H01L2924/0002 ,  Y10S977/833 ,  H01L2924/00

Abstract: An embodiment of the present invention described and shown in the specification and drawings is a process and a package for facilitating cooling and grounding of a semiconductor die using carbon nanotubes in a thermal interface layer between the die and a thermal management aid. The embodiments that are disclosed have the carbon nanotubes positioned and sized to utilize their high thermal and electrical conductance to facilitate the flow of heat and current to the thermal management aid. One embodiment disclosed has the carbon nanotubes mixed with a paste matrix before being applied. Another disclosed embodiment has the carbon nanotubes grown on the surface of the semiconductor die.

Abstract translation: 在说明书和附图中描述和示出的本发明的实施例是用于在模具和热管理辅助器之间的热界面层中使用碳纳米管促进半导体管芯的冷却和接地的方法和封装。 所公开的实施例具有碳纳米管的定位和尺寸以利用其高的热和电导率来促进热和电流流向热管理辅助装置。 所公开的一个实施例在施加之前碳纳米管与糊状基质混合。 另一个公开的实施例具有在半导体管芯的表面上生长的碳纳米管。

公开(公告)号：US20030218235A1

公开(公告)日：2003-11-27

申请号：US10152524

申请日：2002-05-21

Applicant: Intel Corporation

Inventor： Damion T. Searls ,  Weston C. Roth ,  James Daniel Jackson

IPC: H01L029/00 ,  H01L023/52 ,  H01L023/48 ,  H01L029/40

CPC classification number: H01L24/81 ,  H01L23/642 ,  H01L24/16 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/145 ,  H05K2201/10515 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10S257/924 ,  Y10S438/957

Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.

Abstract translation: 封装高性能微电子器件（例如处理器）的系统响应元件瞬变。 在一个实施例中，该系统包括设置在Vcc电凸起和Vss电凸起之间的去耦电容器。 去耦电容器具有Vcc和Vss端子。 Vcc和Vss端子与Vcc电气凸块和Vss电气凸块共享电气垫。 创建一个简单的电流循环，可以改善系统的功率传递。

公开(公告)号：US20040155335A1

公开(公告)日：2004-08-12

申请号：US10774955

申请日：2004-02-09

Applicant: Intel Corporation

Inventor： Damion T. Searls ,  Weston C. Roth ,  James Daniel Jackson

IPC: H01L023/48

CPC classification number: H01L24/81 ,  H01L23/642 ,  H01L24/16 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/145 ,  H05K2201/10515 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10S257/924 ,  Y10S438/957

Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.