公开(公告)号：US20190205200A1

公开(公告)日：2019-07-04

申请号：US16234539

申请日：2018-12-27

申请人： Intel Corporation

发明人： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

IPC分类号： G06F11/07 ,  G06F12/08 ,  G06F9/30

CPC分类号： G06F11/0784 ,  G06F9/30036 ,  G06F9/30043 ,  G06F12/08

摘要： A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

公开(公告)号：US10255126B2

公开(公告)日：2019-04-09

申请号：US15893982

申请日：2018-02-12

申请人： Intel Corporation

发明人： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

IPC分类号： G06F9/30 ,  G06F11/07 ,  G06F12/08

摘要： A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

公开(公告)号：US09727476B2

公开(公告)日：2017-08-08

申请号：US14635403

申请日：2015-03-02

申请人： Intel Corporation

发明人： Boris Ginzburg ,  Oleg Margulis

IPC分类号： G09G5/36 ,  G06F12/0875 ,  G06T1/60

CPC分类号： G06F12/0875 ,  G06F2212/452 ,  G06T1/60

摘要： A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a 2-D image stored in a memory coupled to the processor. The 2-D cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a 2-D structure of the 2-D image.

公开(公告)号：US08866831B2

公开(公告)日：2014-10-21

申请号：US14172493

申请日：2014-02-04

申请人： Intel Corporation

发明人： Boris Ginzburg

IPC分类号： G06F15/167 ,  G06F15/16 ,  G09G5/39 ,  G06F12/12 ,  G06T1/60 ,  G06F12/10 ,  G06F3/14 ,  G09G5/36

CPC分类号： G06T1/60 ,  G06F3/14 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/1063 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/656 ,  G06T2200/28 ,  G09G5/363 ,  G09G5/39 ,  G09G2360/121 ,  G09G2360/125

摘要： In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

公开(公告)号：US08669992B2

公开(公告)日：2014-03-11

申请号：US13895723

申请日：2013-05-16

申请人： Intel Corporation

发明人： Boris Ginzburg

IPC分类号： G06F15/167 ,  G06F15/16

CPC分类号： G06T1/60 ,  G06F3/14 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/1063 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/656 ,  G06T2200/28 ,  G09G5/363 ,  G09G5/39 ,  G09G2360/121 ,  G09G2360/125

摘要： In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有设备处理器和设备存储器的设备。 该设备可以连接到具有主机处理器和主机内存的主机。 两个存储器都可以具有页表以将虚拟地址映射到相应存储器的物理地址，并且两个存储器可以以用户级应用程序显示为单个虚拟存储器空间。 描述和要求保护其他实施例。

公开(公告)号：US20200218568A1

公开(公告)日：2020-07-09

申请号：US16729760

申请日：2019-12-30

申请人： Intel Corporation

发明人： Ronny Ronen ,  Boris Ginzburg ,  Eliezer Weissmann

IPC分类号： G06F9/48 ,  G06F9/38 ,  G06F15/78 ,  G06F12/1027

摘要： An apparatus is described having multiple cores, each core having: a) a CPU; b) an accelerator; and, c) a controller and a plurality of order buffers coupled between the CPU and the accelerator. Each of the order buffers is dedicated to a different one of the CPU's threads. Each one of the order buffers is to hold one or more requests issued to the accelerator from its corresponding thread. The controller is to control issuance of the order buffers' respective requests to the accelerator.

公开(公告)号：US10120691B2

公开(公告)日：2018-11-06

申请号：US15214270

申请日：2016-07-19

申请人： Intel Corporation

发明人： Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann ,  Karthikeyan Vaithianathan ,  Ehud Cohen

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

摘要： In one embodiment, a processor includes an accelerator, a decoder to decode a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction, and an execution unit to execute the first decoded instruction to, for a thread executing on the accelerator that is to be placed in an inactive state, cause a save of context information for the thread, and a save of a vector identifying the accelerator corresponding to the context information, and execute the second decoded instruction to read the vector to determine the accelerator to restore saved context information into for the thread, read the saved context information, and restore the saved context information into the accelerator.

公开(公告)号：US20170024210A1

公开(公告)日：2017-01-26

申请号：US15175881

申请日：2016-06-07

申请人： Intel Corporation

发明人： Efraim Rotem ,  Eliezer Weissmann ,  Michael Mishaeli ,  Boris Ginzburg ,  Alon Naveh

IPC分类号： G06F9/30 ,  G06F9/46 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/461

摘要： A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.

摘要翻译： 处理器可以节省微架构上下文以提高代码执行和电源管理的效率。 执行保存指令以在停止进程的执行的上下文切换时将微架构状态和处理器的体系结构状态存储在存储器的公共缓冲器中。 微架构状态包含执行该过程所产生的性能数据。 执行恢复指令以在恢复执行该过程时从公共缓冲器检索微架构状态和架构状态。 电源管理硬件然后使用微架构状态作为恢复执行的中间起点。

公开(公告)号：US09250906B2

公开(公告)日：2016-02-02

申请号：US14840014

申请日：2015-08-30

申请人： Intel Corporation

发明人： Gadi Haber ,  Konstantin Kostya Levit-Gurevich ,  Esfir Natanzon ,  Boris Ginzburg ,  Aya Elhanan ,  Moshe Maury Bach ,  Igor Breger

IPC分类号： G06F9/30 ,  G06F12/08 ,  G06F9/00

CPC分类号： G06F9/30181 ,  G06F8/52 ,  G06F9/30145 ,  G06F9/45558 ,  G06F9/467 ,  G06F12/0875 ,  G06F2212/452

摘要： Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.

公开(公告)号：US11275637B2

公开(公告)日：2022-03-15

申请号：US16994269

申请日：2020-08-14

申请人： Intel Corporation

发明人： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

IPC分类号： G06F11/07 ,  G06F12/08 ,  G06F9/30

摘要： A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.